1#
2# Seagate FireCuda Gaming SSD (FaZe) board
3#
4
5# An external debug probe must be connected to the SWD port (4-pins J2 header).
6# Here we assume that a ST-LINK in-circuit debugger/programmer is used. You may
7# have to replace it with your own interface here.
8source [find interface/stlink.cfg]
9
10# NXP LPC11U24 Cortex-M0 with 128KB Flash and 20KB + 4KB SRAM
11set WORKAREASIZE 0x5000
12
13set CPUTAPID 0x0bc11477
14
15source [find target/lpc11xx.cfg]
16
17# This ensures that the interrupt vectors (0x0000-0x0200) are re-mapped to
18# flash after the "reset halt" command. Else the load/verify functions won't
19# work correctly.
20#
21# Table 8. System memory remap register (SYSMEMREMAP, address 0x40048000) bit
22#          description
23# Bit Symbol Value Description
24# 1:0 MAP          System memory remap
25#            0x0   Boot Loader Mode. Interrupt vectors are re-mapped to
26#            Boot ROM.
27#            0x1   User RAM Mode. Interrupt vectors are re-mapped to
28#            Static RAM.
29#            0x2   User Flash Mode. Interrupt vectors are not re-mapped
30#            and reside in Flash.
31# 31:2 -     -     Reserved.
32$_TARGETNAME configure -event reset-end {
33	 mww 0x40048000 0x02
34}
35
36# Enable Zephyr thread awareness.
37$_TARGETNAME configure -rtos Zephyr
38
39adapter_khz 100
40