1/*
2 * Copyright (c) 2021 Cypress Semiconductor Corporation.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6/dts-v1/;
7#include <infineon/psoc6/mpns/CY8C624ABZI_S2D44.dtsi>
8#include <infineon/psoc6/system_clocks.dtsi>
9#include "cy8cproto_062_4343w-common.dtsi"
10#include "cy8cproto_062_4343w-pinctrl.dtsi"
11
12/ {
13	model = "cy8cproto_062_4343w with an Cypress PSoC™ 6 SoC";
14	compatible = "cypress,cy8cproto_062_4343w", "cypress,PSoC6";
15
16	aliases {
17		uart-5 = &uart5;
18		i2c-0 = &i2c3;
19		watchdog0 = &watchdog0;
20	};
21
22	chosen {
23		zephyr,sram = &sram0;
24		zephyr,flash = &flash0;
25		zephyr,console = &uart5;
26		zephyr,shell-uart = &uart5;
27		zephyr,bt_uart = &uart2;
28	};
29};
30
31&counter0_0 {
32	status = "okay";
33};
34
35uart5: &scb5 {
36	compatible = "infineon,cat1-uart";
37	status = "okay";
38	current-speed = <115200>;
39
40	pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>;
41	pinctrl-names = "default";
42};
43
44uart2: &scb2 {
45	compatible = "infineon,cat1-uart";
46	status = "okay";
47	/* The UART bus speed (current_speed) for zephyr_bt_uart should be the same
48	 * as the default baudrate defined in CYW43xx firmware (default 115200).
49	 */
50
51	current-speed = <115200>;
52
53	/* HCI-UART pins*/
54	pinctrl-0 = <&p3_1_scb2_uart_tx &p3_0_scb2_uart_rx &p3_2_scb2_uart_rts &p3_3_scb2_uart_cts>;
55	pinctrl-names = "default";
56
57	bt-hci {
58		status = "okay";
59		compatible = "infineon,cyw43xxx-bt-hci";
60		bt-reg-on-gpios = <&gpio_prt3 4 (GPIO_ACTIVE_HIGH)>;
61
62		/* Configuration UART speeds for firmware download (fw-download-speed) and
63		 * HCI operation (hci-operation-speed).
64		 * If hci-operation-speed or fw-download-speed are not defined in bt-hci{...}
65		 * node, cyw43xx driver will use bus/current-speed as default speed.
66		 */
67		fw-download-speed = <3000000>;
68	};
69};
70
71/* System clock configuration */
72&fll0 {
73	status = "okay";
74	clock-frequency = <100000000>;
75};
76
77&clk_hf0 {
78	clock-div = <1>;
79	clocks = <&fll0>;
80};
81
82/* CM4 core clock = 100MHz
83 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
84 */
85&clk_fast {
86	clock-div = <1>;
87};
88
89/* CM0+ core clock = 50MHz
90 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
91 */
92&clk_slow {
93	clock-div = <2>;
94};
95
96/* PERI core clock = 100MHz
97 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
98 */
99&clk_peri {
100	clock-div = <1>;
101};
102
103i2c3: &scb3 {
104	compatible = "infineon,cat1-i2c";
105
106	/* I2C pins */
107	pinctrl-0 = <&p6_0_scb3_i2c_scl &p6_1_scb3_i2c_sda>;
108	pinctrl-names = "default";
109};
110
111&watchdog0 {
112	status = "okay";
113};
114