1/* 2 * Copyright (c) 2019-2023 Nordic Semiconductor ASA 3 * Copyright (c) 2021-2023 Laird Connectivity 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7#include "bl5340_dvk_cpuapp_common-pinctrl.dtsi" 8#include <zephyr/dt-bindings/input/input-event-codes.h> 9 10/ { 11 chosen { 12 zephyr,console = &uart0; 13 zephyr,shell-uart = &uart0; 14 zephyr,uart-mcumgr = &uart0; 15 zephyr,bt-mon-uart = &uart0; 16 zephyr,bt-c2h-uart = &uart0; 17 zephyr,display = &ili9340; 18 zephyr,bt-hci-rpmsg-ipc = &ipc0; 19 }; 20 21 /* Main LEDs and buttons are on an I2C TCA9538 GPIO port expander */ 22 /* Note TCA9538 does not have configurable internal pull ups/ downs */ 23 buttons { 24 compatible = "gpio-keys"; 25 boot_button0: boot_button { 26 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 27 label = "Bootloader button (S4)"; 28 zephyr,code = <INPUT_KEY_0>; 29 }; 30 31 button1: button_1 { 32 gpios = <&gpio_exp0 0 GPIO_ACTIVE_LOW>; 33 label = "Push button switch 1 (S1)"; 34 zephyr,code = <INPUT_KEY_1>; 35 }; 36 37 button2: button_2 { 38 gpios = <&gpio_exp0 1 GPIO_ACTIVE_LOW>; 39 label = "Push button switch 2 (S2)"; 40 zephyr,code = <INPUT_KEY_2>; 41 }; 42 43 button3: button_3 { 44 gpios = <&gpio_exp0 2 GPIO_ACTIVE_LOW>; 45 label = "Push button switch 3 (S9)"; 46 zephyr,code = <INPUT_KEY_3>; 47 }; 48 49 button4: button_4 { 50 gpios = <&gpio_exp0 3 GPIO_ACTIVE_LOW>; 51 label = "Push button switch 4 (S10)"; 52 zephyr,code = <INPUT_KEY_4>; 53 }; 54 }; 55 56 leds { 57 compatible = "gpio-leds"; 58 led1: led_1 { 59 gpios = <&gpio_exp0 4 GPIO_ACTIVE_LOW>; 60 label = "Blue LED 1"; 61 }; 62 led2: led_2 { 63 gpios = <&gpio_exp0 5 GPIO_ACTIVE_LOW>; 64 label = "Blue LED 2"; 65 }; 66 led3: led_3 { 67 gpios = <&gpio_exp0 6 GPIO_ACTIVE_LOW>; 68 label = "Blue LED 3"; 69 }; 70 led4: led_4 { 71 gpios = <&gpio_exp0 7 GPIO_ACTIVE_LOW>; 72 label = "Blue LED 4"; 73 }; 74 }; 75 76 lvgl_pointer { 77 compatible = "zephyr,lvgl-pointer-input"; 78 input = <&ft5336>; 79 swap-xy; 80 invert-x; 81 invert-y; 82 }; 83 84 gpio_fwd: nrf-gpio-forwarder { 85 compatible = "nordic,nrf-gpio-forwarder"; 86 status = "okay"; 87 uart { 88 gpios = <&gpio1 8 0>, <&gpio1 10 0>, <&gpio1 7 0>, <&gpio1 9 0>; 89 }; 90 }; 91 92 /* These aliases are provided for compatibility with samples */ 93 aliases { 94 led0 = &led1; 95 led1 = &led2; 96 led2 = &led3; 97 led3 = &led4; 98 sw0 = &button1; 99 sw1 = &button2; 100 sw2 = &button3; 101 sw3 = &button4; 102 mcuboot-button0 = &button1; 103 mcuboot-led0 = &led1; 104 sdhc0 = &sdhc0; 105 watchdog0 = &wdt0; 106 accel0 = &lis3dh; 107 bbram0 = &extrtc0; 108 spi-flash0 = &mx25r64; 109 }; 110}; 111 112&adc { 113 status = "okay"; 114}; 115 116&gpiote { 117 status = "okay"; 118}; 119 120&gpio0 { 121 status = "okay"; 122}; 123 124&gpio1 { 125 status = "okay"; 126}; 127 128&i2c1 { 129 compatible = "nordic,nrf-twim"; 130 status = "okay"; 131 132 pinctrl-0 = <&i2c1_default>; 133 pinctrl-1 = <&i2c1_sleep>; 134 pinctrl-names = "default", "sleep"; 135 at24c256@50 { 136 compatible = "atmel,at24"; 137 reg = <0x50>; 138 size = <32768>; 139 pagesize = <64>; 140 address-width = <16>; 141 timeout = <10>; 142 }; 143 144 lis3dh: lis3dh@18 { 145 compatible = "st,lis2dh"; 146 reg = <0x18>; 147 irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>, <&gpio0 24 GPIO_ACTIVE_HIGH>; 148 }; 149 150 ft5336: ft5336@38 { 151 compatible = "focaltech,ft5336"; 152 reg = <0x38>; 153 int-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; 154 }; 155 156 bme680@76 { 157 compatible = "bosch,bme680"; 158 reg = <0x76>; 159 }; 160 161 dac0: mcp4725@60 { 162 compatible = "microchip,mcp4725"; 163 reg = <0x60>; 164 #io-channel-cells = <1>; 165 }; 166 167 extrtc0: mcp7940n@6f { 168 compatible = "microchip,mcp7940n"; 169 reg = <0x6f>; 170 status = "okay"; 171 }; 172 173 gpio_exp0: tca9538@70 { 174 compatible = "ti,tca9538"; 175 reg = <0x70>; 176 gpio-controller; 177 #gpio-cells = <2>; 178 ngpios = <8>; 179 nint-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 180 }; 181}; 182 183&spi2 { 184 compatible = "nordic,nrf-spim"; 185 status = "okay"; 186 cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; 187 188 pinctrl-0 = <&spi2_default>; 189 pinctrl-1 = <&spi2_sleep>; 190 pinctrl-names = "default", "sleep"; 191 enc424j600@0 { 192 compatible = "microchip,enc424j600"; 193 reg = <0>; 194 spi-max-frequency = <8000000>; 195 int-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; 196 }; 197}; 198 199&spi3 { 200 compatible = "nordic,nrf-spim"; 201 status = "okay"; 202 cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 203 204 pinctrl-0 = <&spi3_default>; 205 pinctrl-1 = <&spi3_sleep>; 206 pinctrl-names = "default", "sleep"; 207 sdhc0: sdhc@0 { 208 reg = <0>; 209 compatible = "zephyr,sdhc-spi-slot"; 210 status = "okay"; 211 spi-max-frequency = <8000000>; 212 mmc { 213 compatible = "zephyr,sdmmc-disk"; 214 status = "okay"; 215 }; 216 }; 217}; 218 219&spi4 { 220 compatible = "nordic,nrf-spim"; 221 status = "okay"; 222 cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; 223 224 pinctrl-0 = <&spi4_default>; 225 pinctrl-1 = <&spi4_sleep>; 226 pinctrl-names = "default", "sleep"; 227 ili9340: ili9340@0 { 228 compatible = "ilitek,ili9340"; 229 reg = <0>; 230 spi-max-frequency = <32000000>; 231 reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 232 cmd-data-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; 233 rotation = <270>; 234 width = <320>; 235 height = <240>; 236 }; 237}; 238 239&uart0 { 240 status = "okay"; 241 current-speed = <115200>; 242 pinctrl-0 = <&uart0_default>; 243 pinctrl-1 = <&uart0_sleep>; 244 pinctrl-names = "default", "sleep"; 245}; 246 247&pwm0 { 248 status = "okay"; 249 pinctrl-0 = <&pwm0_default>; 250 pinctrl-1 = <&pwm0_sleep>; 251 pinctrl-names = "default", "sleep"; 252}; 253 254&qspi { 255 status = "okay"; 256 pinctrl-0 = <&qspi_default>; 257 pinctrl-1 = <&qspi_sleep>; 258 pinctrl-names = "default", "sleep"; 259 mx25r64: mx25r6435f@0 { 260 compatible = "nordic,qspi-nor"; 261 reg = <0>; 262 /* MX25R64 supports only pp and pp4io */ 263 writeoc = "pp4io"; 264 /* MX25R64 supports all readoc options */ 265 readoc = "read4io"; 266 sck-frequency = <8000000>; 267 jedec-id = [c2 28 17]; 268 sfdp-bfp = [ 269 e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb 270 ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 271 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 272 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff 273 ]; 274 size = <67108864>; 275 has-dpd; 276 t-enter-dpd = <10000>; 277 t-exit-dpd = <35000>; 278 }; 279}; 280 281&flash0 { 282 partitions { 283 compatible = "fixed-partitions"; 284 #address-cells = <1>; 285 #size-cells = <1>; 286 287 /* 64K */ 288 boot_partition: partition@0 { 289 label = "mcuboot"; 290 reg = <0x00000000 0x00010000>; 291 }; 292 /* 640K */ 293 slot0_partition: partition@10000 { 294 label = "image-0"; 295 }; 296 /* 256K */ 297 slot0_ns_partition: partition@b0000 { 298 label = "image-0-nonsecure"; 299 }; 300 301 /* 302 * The flash starting at 0x000f8000 and ending at 303 * 0x000fffff is reserved for use by the application. 304 */ 305 306 /* 307 * Storage partition will be used by FCB/NVS 308 * if enabled. 32K 309 */ 310 storage_partition: partition@f8000 { 311 label = "storage"; 312 reg = <0x000f8000 0x00008000>; 313 }; 314 }; 315}; 316 317&mx25r64 { 318 partitions { 319 compatible = "fixed-partitions"; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 323 /* 640K */ 324 slot1_partition: partition@0 { 325 label = "image-1"; 326 }; 327 /* 256K */ 328 slot1_ns_partition: partition@A0000 { 329 label = "image-1-nonsecure"; 330 }; 331 /* 128K */ 332 scratch_partition: partition@e0000 { 333 label = "image-scratch"; 334 reg = <0x000e0000 0x00020000>; 335 }; 336 /* 7MB */ 337 lfs_partition: partition@100000 { 338 label = "lfs_storage"; 339 reg = <0x00100000 0x00700000>; 340 }; 341 }; 342}; 343 344/ { 345 reserved-memory { 346 #address-cells = <1>; 347 #size-cells = <1>; 348 ranges; 349 350 sram0_image: image@20000000 { 351 /* Zephyr image(s) memory */ 352 }; 353 354 sram0_s: image_s@20000000 { 355 /* Secure image memory */ 356 }; 357 358 sram0_ns: image_ns@20040000 { 359 /* Non-Secure image memory */ 360 }; 361 }; 362}; 363 364/* Include partition configuration file */ 365#include "bl5340_dvk_cpuapp_partition_conf.dtsi" 366
