1/*
2 * Copyright (c) 2019 Intel Corporation
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#include <zephyr/arch/x86/multiboot.h>
7#include <zephyr/devicetree.h>
8
9/*
10 * This is included by ia32/crt0.S and intel64/locore.S
11 * at their 32-bit entry points to cover common ground.
12 */
13
14#ifdef CONFIG_MULTIBOOT_INFO
15        /*
16         * If we were loaded by a multiboot-compliant loader, then EAX
17         * contains MULTIBOOT_EAX_MAGIC and EBX points to a valid 'struct
18         * multiboot_info'; otherwise EBX is just junk. Check EAX early
19	 * before it's clobbered and leave a sentinel (0) in EBX if invalid.
20	 * The valid in EBX will be the argument to z_x86_prep_c(), so the
21	 * subsequent code must, of course, be sure to preserve it meanwhile.
22	 */
23
24	cmpl $MULTIBOOT_EAX_MAGIC, %eax
25	je 1f
26	xorl %ebx, %ebx
271:
28#endif
29
30#ifdef CONFIG_PIC_DISABLE
31	/*
32	 * "Disable" legacy i8259 interrupt controllers. Note that we
33	 * can't actually disable them, but we mask all their interrupt
34	 * sources which is effectively the same thing (almost).
35	 */
36
37	movb $0xff, %al
38	outb %al, $0x21
39	outb %al, $0xA1
40#endif
41
42#ifdef CONFIG_MULTIBOOT
43	jmp 1f
44
45	.align 4
46	.long MULTIBOOT_HEADER_MAGIC
47	.long MULTIBOOT_HEADER_FLAGS
48	.long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
49#if DT_HAS_COMPAT_STATUS_OKAY(intel_multiboot_framebuffer)
50	.fill 5,4,0							/* (unused exec layout) */
51	.long 0								/* linear graphics mode */
52	.long DT_PROP(DT_INST(0, intel_multiboot_framebuffer), width)	/* width */
53	.long DT_PROP(DT_INST(0, intel_multiboot_framebuffer), height)	/* height */
54	.long 32							/* depth */
55#endif
561:
57#endif
58