1# Memory Protection Unit (MPU) configuration options
2
3#Copyright (c) 2017 Linaro Limited.
4#Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
5
6# SPDX-License-Identifier: Apache-2.0
7
8if CPU_HAS_MPU
9
10config ARM_MPU
11	bool "ARM MPU Support"
12	select THREAD_STACK_INFO
13	select MPU
14	select SRAM_REGION_PERMISSIONS
15	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
16	default y
17	help
18	  MPU implements Memory Protection Unit.
19
20	  Notes:
21	  The ARMv8-R MPU architecture requires a power-of-two alignment
22	  of MPU region base address and size(64 bytes aligned).
23
24	  The ARMv8-R MPU requires the active MPU regions be non-overlapping.
25	  As a result of this, the ARMv8-R MPU needs to fully partition the
26	  memory map when programming dynamic memory regions (e.g. PRIV stack
27	  guard, user thread stack, and application memory domains), if the
28	  system requires PRIV access policy different from the access policy
29	  of the ARMv8-R background memory map. The application developer may
30	  enforce full PRIV (kernel) memory partition by enabling the
31	  CONFIG_MPU_GAP_FILLING option.
32	  By not enforcing full partition, MPU may leave part of kernel
33	  SRAM area covered only by the default ARMv8-R memory map. This
34	  is fine for User Mode, since the background ARM map does not
35	  allow nPRIV access at all. However, since the background map
36	  policy allows instruction fetches by privileged code, forcing
37	  this Kconfig option off prevents the system from directly
38	  triggering MemManage exceptions upon accidental attempts to
39	  execute code from SRAM in XIP builds.
40	  Since this does not compromise User Mode, we make the skipping
41	  of full partitioning the default behavior for the ARMv8-R MPU
42	  driver.
43
44config ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
45	int
46	default 64 if ARM_MPU
47	default 4
48	help
49	  Minimum size (and alignment) of an ARM MPU region. Use this
50	  symbol to guarantee minimum size and alignment of MPU regions.
51	  A minimum 4-byte alignment is enforced in ARM builds without
52	  support for Memory Protection.
53
54if ARM_MPU
55
56config MPU_ALLOW_FLASH_WRITE
57	bool "Add MPU access to write to flash"
58	help
59	  Enable this to allow MPU RWX access to flash memory
60
61endif # ARM_MPU
62
63endif # CPU_HAS_MPU
64