1/*
2 * Copyright (c) 2019 - 2020 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR)
8/*
9 * In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the
10 * exc_vector_table (i.e. _vector_start) during initialization. Therefore,
11 * exc_vector_table must respect the alignment requirements of VTOR.TBLOFF
12 * described below.
13 */
14
15#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
16/* VTOR bits 0:7 are reserved (RES0). This requires that the base address
17 * of the vector table is 64-word aligned.
18 */
19. = ALIGN( 1 << LOG2CEIL(4 * 64) );
20#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
21/* VTOR bits 0:6 are reserved (RES0). This requires that the base address
22 * of the vector table is 32-word aligned.
23 */
24. = ALIGN( 1 << LOG2CEIL(4 * 32) );
25#else
26#error "Unsupported architecture variant"
27#endif
28
29/* When setting TBLOFF in VTOR we must align the offset to the number of
30 * exception entries in the vector table. The minimum alignment of 32 words
31 * is sufficient for the 16 ARM Core exceptions and up to 16 HW interrupts.
32 * For more than 16 HW interrupts, we adjust the alignment by rounding up
33 * to the next power of two; this restriction guarantees a functional VTOR
34 * setting in any Cortex-M implementation (might not be required in every
35 * Cortex-M processor).
36 */
37. = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );
38#endif
39
40#ifdef CONFIG_ARM_ZIMAGE_HEADER
41/*
42 * For AArch32 (A/R), VBAR has Bits [4:0] = RES0.
43 * For AArch32 (M), VTOR has Bits [6:0] = RES0. Thus, vector start address
44 * should be aligned in such a way so that it satisfies the requirements of
45 * VBAR and VTOR ie Bits [6:0] = 0.
46 */
47. = ALIGN( 0x80 );
48#endif
49
50_vector_start = .;
51KEEP(*(.exc_vector_table))
52KEEP(*(".exc_vector_table.*"))
53
54KEEP(*(.vectors))
55
56_vector_end = .;
57