1/*
2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
3 * Contributors: 2018 Antmicro <www.antmicro.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/toolchain.h>
9
10/* exports */
11GTEXT(__start)
12
13/* imports */
14GTEXT(__initialize)
15GTEXT(_isr_wrapper)
16
17SECTION_FUNC(vectors, __start)
18#if defined(CONFIG_RISCV_GP)
19	/* Initialize global pointer */
20	.option push
21	.option norelax
22	la gp, __global_pointer$
23	.option pop
24#endif
25
26	.option norvc;
27
28#if defined(CONFIG_RISCV_MTVEC_VECTORED_MODE)
29	/*
30	 * Set mtvec (Machine Trap-Vector Base-Address Register)
31	 * to _irq_vector_table (interrupt vector table). Add 1 to base
32	 * address of _irq_vector_table to indicate that vectored mode
33	 * is used (LSB = 0x1). CPU will mask the LSB out of
34	 * the address so that base address of _irq_vector_table is used.
35	 *
36	 * NOTE: _irq_vector_table is 256-byte aligned. Incorrect alignment
37	 *        of _irq_vector_table breaks this code.
38	 */
39	la t0, _irq_vector_table /* Load address of interrupt vector table */
40	addi t0, t0, 1 /* Enable vectored mode by setting LSB */
41
42/* MTVEC_DIRECT_MODE */
43#else
44	/*
45	 * Set mtvec (Machine Trap-Vector Base-Address Register)
46	 * to _isr_wrapper.
47	 */
48	la t0, _isr_wrapper
49#endif
50
51	csrw mtvec, t0
52
53	/* Jump to __reset */
54	tail __reset
55