1module ghrd_10m50da_top ( 2 //Clock and Reset 3 input wire clk_50, 4 //input wire clk_ddr3_100_p, 5 input wire fpga_reset_n, 6 //QSPI 7 output wire qspi_clk, 8 inout wire[3:0] qspi_io, 9 output wire qspi_csn, 10 //ddr3 11 //output wire [13:0] mem_a, 12 //output wire [2:0] mem_ba, 13 //inout wire [0:0] mem_ck, 14 //inout wire [0:0] mem_ck_n, 15 //output wire [0:0] mem_cke, 16 //output wire [0:0] mem_cs_n, 17 //output wire [0:0] mem_dm, 18 //output wire [0:0] mem_ras_n, 19 //output wire [0:0] mem_cas_n, 20 //output wire [0:0] mem_we_n, 21 //output wire mem_reset_n, 22 ///inout wire [7:0] mem_dq, 23 //inout wire [0:0] mem_dqs, 24 //inout wire [0:0] mem_dqs_n, 25 //output wire [0:0] mem_odt, 26 //i2c 27 inout wire i2c_sda, 28 inout wire i2c_scl, 29 //spi 30 input wire spi_miso, 31 output wire spi_mosi, 32 output wire spi_sclk, 33 output wire spi_ssn, 34 //16550 UART 35 input wire uart_rx, 36 output wire uart_tx, 37 output wire [4:0] user_led 38); 39//Heart-beat counter 40reg [25:0] heart_beat_cnt; 41 42//DDR3 interface assignments 43//wire local_init_done; 44//wire local_cal_success; 45//wire local_cal_fail; 46 47//i2c interface 48wire i2c_serial_sda_in ; 49wire i2c_serial_scl_in ; 50wire i2c_serial_sda_oe ; 51wire i2c_serial_scl_oe ; 52assign i2c_serial_scl_in = i2c_scl; 53assign i2c_scl = i2c_serial_scl_oe ? 1'b0 : 1'bz; 54 55assign i2c_serial_sda_in = i2c_sda; 56assign i2c_sda = i2c_serial_sda_oe ? 1'b0 : 1'bz; 57 58//assign system_resetn = fpga_reset_n & local_init_done; 59 60// SoC sub-system module 61ghrd_10m50da ghrd_10m50da_inst ( 62 .clk_clk (clk_50), 63 //.ref_clock_bridge_in_clk_clk (clk_ddr3_100_p), 64 .reset_reset_n (fpga_reset_n), 65 //.mem_resetn_in_reset_reset_n (fpga_reset_n ), // mem_resetn_in_reset.reset_n 66 .ext_flash_qspi_pins_data (qspi_io), 67 .ext_flash_qspi_pins_dclk (qspi_clk), 68 .ext_flash_qspi_pins_ncs (qspi_csn), 69 //.memory_mem_a (mem_a[12:0] ), // memory.mem_a 70 //.memory_mem_ba (mem_ba ), // .mem_ba 71 //.memory_mem_ck (mem_ck ), // .mem_ck 72 //.memory_mem_ck_n (mem_ck_n ), // .mem_ck_n 73 //.memory_mem_cke (mem_cke ), // .mem_cke 74 //.memory_mem_cs_n (mem_cs_n ), // .mem_cs_n 75 //.memory_mem_dm (mem_dm ), // .mem_dm 76 //.memory_mem_ras_n (mem_ras_n ), // .mem_ras_n 77 //.memory_mem_cas_n (mem_cas_n ), // .mem_cas_n 78 //.memory_mem_we_n (mem_we_n ), // .mem_we_n 79 //.memory_mem_reset_n (mem_reset_n ), // .mem_reset_n 80 //.memory_mem_dq (mem_dq ), // .mem_dq 81 //.memory_mem_dqs (mem_dqs ), // .mem_dqs 82 //.memory_mem_dqs_n (mem_dqs_n ), // .mem_dqs_n 83 //.memory_mem_odt (mem_odt ), // .mem_odt 84 //.mem_if_ddr3_emif_0_status_local_init_done (local_init_done ), // mem_if_ddr3_emif_0_status.local_init_done 85 //.mem_if_ddr3_emif_0_status_local_cal_success (local_cal_success ), // .local_cal_success 86 //.mem_if_ddr3_emif_0_status_local_cal_fail (local_cal_fail ), // .local_cal_fail 87 //i2c 88 .i2c_0_i2c_serial_sda_in (i2c_serial_sda_in), 89 .i2c_0_i2c_serial_scl_in (i2c_serial_scl_in), 90 .i2c_0_i2c_serial_sda_oe (i2c_serial_sda_oe), 91 .i2c_0_i2c_serial_scl_oe (i2c_serial_scl_oe), 92 //spi 93 .spi_0_external_MISO (spi_miso), // spi_0_external.MISO 94 .spi_0_external_MOSI (spi_mosi), // .MOSI 95 .spi_0_external_SCLK (spi_sclk), // .SCLK 96 .spi_0_external_SS_n (spi_ssn), // .SS_n 97 //pio 98 .led_external_connection_export (user_led[3:0]), 99 //16550 UART 100 .a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin 101 .a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout 102 .a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe 103 104); 105 106//DDR3 Address Bit #13 is not available for DDR3 SDRAM A (64Mx16) 107//assign mem_a[13] = 1'b0; 108 109//Heart beat by 50MHz clock 110always @(posedge clk_50 or negedge fpga_reset_n) 111 if (!fpga_reset_n) 112 heart_beat_cnt <= 26'h0; //0x3FFFFFF 113 else 114 heart_beat_cnt <= heart_beat_cnt + 1'b1; 115 116assign user_led[4] = heart_beat_cnt[25]; 117 118 119endmodule 120 121 122
