1 /*
2 * Copyright (c) 2019 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief System/hardware module for STM32H7 CM7 processor
10 */
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/device.h>
14 #include <zephyr/init.h>
15 #include <zephyr/irq.h>
16 #include <soc.h>
17 #include <stm32_ll_bus.h>
18 #include <stm32_ll_pwr.h>
19 #include <stm32_ll_rcc.h>
20 #include <stm32_ll_system.h>
21 #include <zephyr/arch/cpu.h>
22 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
23 #include <zephyr/arch/arm/aarch32/nmi.h>
24 #include "stm32_hsem.h"
25
26 #if defined(CONFIG_STM32H7_DUAL_CORE)
stm32h7_m4_wakeup(void)27 static int stm32h7_m4_wakeup(void)
28 {
29
30 /* HW semaphore and SysCfg Clock enable */
31 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
32 LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
33
34 if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) {
35 /* Cortex-M4 is waiting for end of system initialization made by
36 * Cortex-M7. This initialization is now finished,
37 * then Cortex-M7 takes HSEM so that CM4 can continue running.
38 */
39 LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID);
40 } else if (IS_ENABLED(CONFIG_STM32H7_BOOT_M4_AT_INIT)) {
41 /* CM4 is not started at boot, start it now */
42 LL_RCC_ForceCM4Boot();
43 }
44
45 return 0;
46 }
47 #endif /* CONFIG_STM32H7_DUAL_CORE */
48
49 /**
50 * @brief Perform basic hardware initialization at boot.
51 *
52 * This needs to be run from the very beginning.
53 * So the init priority has to be 0 (zero).
54 *
55 * @return 0
56 */
stm32h7_init(void)57 static int stm32h7_init(void)
58 {
59 uint32_t key;
60
61
62 key = irq_lock();
63
64 SCB_EnableICache();
65
66 if (IS_ENABLED(CONFIG_DCACHE)) {
67 if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
68 SCB_EnableDCache();
69 }
70 }
71
72 /* Install default handler that simply resets the CPU
73 * if configured in the kernel, NOP otherwise
74 */
75 NMI_INIT();
76
77 irq_unlock(key);
78
79 /* Update CMSIS SystemCoreClock variable (HCLK) */
80 /* At reset, system core clock is set to 64 MHz from HSI */
81 SystemCoreClock = 64000000;
82
83 /* Power Configuration */
84 #if !defined(SMPS) && \
85 (defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS) || \
86 defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO) || \
87 defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO) || \
88 defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
89 defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
90 defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT) || \
91 defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT))
92 #error Unsupported configuration: Selected SoC do not support SMPS
93 #endif
94 #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
95 LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
96 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
97 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
98 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
99 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
100 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
101 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
102 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
103 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
104 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
105 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
106 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
107 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
108 #elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
109 LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
110 #else
111 LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
112 #endif
113 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
114 while (LL_PWR_IsActiveFlag_VOS() == 0) {
115 }
116
117 /* Errata ES0392 Rev 8:
118 * 2.2.9: Reading from AXI SRAM may lead to data read corruption
119 * Workaround: Set the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
120 * register.
121 * Applicable only to RevY (REV_ID 0x1003)
122 */
123 if (LL_DBGMCU_GetRevisionID() == 0x1003) {
124 MODIFY_REG(GPV->AXI_TARG7_FN_MOD, 0x1, 0x1);
125 }
126
127 return 0;
128 }
129
130 SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0);
131
132
133 #if defined(CONFIG_STM32H7_DUAL_CORE)
134 /* Unlock M4 once system configuration has been done */
135 SYS_INIT(stm32h7_m4_wakeup, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
136 #endif /* CONFIG_STM32H7_DUAL_CORE */
137
