1 /*
2 * Copyright (c) 2017, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief System/hardware module for nxp_lpc54114 platform
10 *
11 * This module provides routines to initialize and support board-level
12 * hardware for the nxp_lpc54114 platform.
13 */
14
15 #include <zephyr/kernel.h>
16 #include <zephyr/device.h>
17 #include <zephyr/init.h>
18 #include <soc.h>
19 #include <zephyr/drivers/uart.h>
20 #include <zephyr/linker/sections.h>
21 #include <zephyr/arch/cpu.h>
22 #include <aarch32/cortex_m/exc.h>
23 #include <fsl_power.h>
24 #include <fsl_clock.h>
25 #include <fsl_common.h>
26 #include <fsl_device_registers.h>
27 #ifdef CONFIG_GPIO_MCUX_LPC
28 #include <fsl_pint.h>
29 #endif
30 #if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC54114_M4)
31 #include <zephyr_image_info.h>
32 /* Memcpy macro to copy segments from secondary core image stored in flash
33 * to RAM section that secondary core boots from.
34 * n is the segment number, as defined in zephyr_image_info.h
35 */
36 #define MEMCPY_SEGMENT(n, _) \
37 memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_ ## n) - ADJUSTED_LMA), \
38 (uint32_t *)(SEGMENT_LMA_ADDRESS_ ## n), \
39 (SEGMENT_SIZE_ ## n))
40 #endif
41
42 /**
43 *
44 * @brief Initialize the system clock
45 *
46 */
47 #define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
48
clock_init(void)49 static ALWAYS_INLINE void clock_init(void)
50 {
51
52 #ifdef CONFIG_SOC_LPC54114_M4
53 /* Set up the clock sources */
54
55 /* Ensure FRO is on */
56 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);
57
58 /*
59 * Switch to FRO 12MHz first to ensure we can change voltage without
60 * accidentally being below the voltage for current speed.
61 */
62 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
63
64 /* Set FLASH wait states for core */
65 CLOCK_SetFLASHAccessCyclesForFreq(CPU_FREQ);
66
67 /* Set up high frequency FRO output to selected frequency */
68 CLOCK_SetupFROClocking(CPU_FREQ);
69
70 /* Set up dividers */
71 /* Set AHBCLKDIV divider to value 1 */
72 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
73
74 /* Set up clock selectors - Attach clocks to the peripheries */
75 /* Switch MAIN_CLK to FRO_HF */
76 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
77
78 /* Attach 12 MHz clock to FLEXCOMM0 */
79 CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
80
81 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay)
82 /* attach 12 MHz clock to FLEXCOMM4 */
83 CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
84
85 /* reset FLEXCOMM for I2C */
86 RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
87 #endif
88
89 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_spi, okay)
90 /* Attach 12 MHz clock to FLEXCOMM5 */
91 CLOCK_AttachClk(kFRO_HF_to_FLEXCOMM5);
92
93 /* reset FLEXCOMM for SPI */
94 RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn);
95 #endif
96
97 #endif /* CONFIG_SOC_LPC54114_M4 */
98 }
99
100 /**
101 *
102 * @brief Perform basic hardware initialization
103 *
104 * Initialize the interrupt controller device drivers.
105 * Also initialize the timer device driver, if required.
106 *
107 * @return 0
108 */
109
nxp_lpc54114_init(void)110 static int nxp_lpc54114_init(void)
111 {
112
113 /* old interrupt lock level */
114 unsigned int oldLevel;
115
116 /* disable interrupts */
117 oldLevel = irq_lock();
118
119 /* Initialize FRO/system clock to 48 MHz */
120 clock_init();
121
122 #ifdef CONFIG_GPIO_MCUX_LPC
123 /* Turn on PINT device*/
124 PINT_Init(PINT);
125 #endif
126
127 /*
128 * install default handler that simply resets the CPU if configured in
129 * the kernel, NOP otherwise
130 */
131 NMI_INIT();
132
133 /* restore interrupt state */
134 irq_unlock(oldLevel);
135
136 return 0;
137 }
138
139 SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);
140
141 #if defined(CONFIG_PLATFORM_SPECIFIC_INIT) && defined(CONFIG_SOC_LPC54114_M0)
142
143 /* M4 core has a custom platform initialization routine in assembly,
144 * but M0 core does not. install one here to call SystemInit.
145 */
z_arm_platform_init(void)146 void z_arm_platform_init(void)
147 {
148 SystemInit();
149 }
150
151 #endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
152
153
154 #if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC54114_M4)
155
156 #define CORE_M0_BOOT_ADDRESS ((void *)CONFIG_SECOND_CORE_BOOT_ADDRESS_MCUX)
157
158 /**
159 *
160 * @brief Slave Init
161 *
162 * This routine boots the secondary core
163 *
164 * @retval 0 on success.
165 *
166 */
167 /* This function is also called at deep sleep resume. */
_slave_init(void)168 int _slave_init(void)
169 {
170 int32_t temp;
171
172
173 /* Enable SRAM2, used by other core */
174 SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK;
175
176 /* Copy second core image to SRAM */
177 LISTIFY(SEGMENT_NUM, MEMCPY_SEGMENT, (;));
178
179 /* Setup the reset handler pointer (PC) and stack pointer value.
180 * This is used once the second core runs its startup code.
181 * The second core first boots from flash (address 0x00000000)
182 * and then detects its identity (Cortex-M0, slave) and checks
183 * registers CPBOOT and CPSTACK and use them to continue the
184 * boot process.
185 * Make sure the startup code for the current core (Cortex-M4) is
186 * appropriate and shareable with the Cortex-M0 core!
187 */
188 SYSCON->CPBOOT = SYSCON_CPBOOT_BOOTADDR(
189 *(uint32_t *)((uint8_t *)CORE_M0_BOOT_ADDRESS + 0x4));
190 SYSCON->CPSTACK = SYSCON_CPSTACK_STACKADDR(
191 *(uint32_t *)CORE_M0_BOOT_ADDRESS);
192
193 /* Reset the secondary core and start its clocks */
194 temp = SYSCON->CPUCTRL;
195 temp |= 0xc0c48000;
196 SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK
197 | SYSCON_CPUCTRL_CM0RSTEN_MASK);
198 SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK)
199 & (~SYSCON_CPUCTRL_CM0RSTEN_MASK);
200
201 return 0;
202 }
203
204 SYS_INIT(_slave_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
205
206 #endif /*CONFIG_SECOND_CORE_MCUX && CONFIG_SOC_LPC54114_M4 */
207
