1# Atmel SAM4S MCU series
2
3# Copyright (c) 2017 Justin Watson
4# Copyright (c) 2018 Vincent van der Locht
5# SPDX-License-Identifier: Apache-2.0
6
7choice
8	prompt "Atmel SAM4S MCU Selection"
9	depends on SOC_SERIES_SAM4S
10
11	config SOC_PART_NUMBER_SAM4S16C
12		bool "SAM4S16C"
13
14	config SOC_PART_NUMBER_SAM4SA16C
15		bool "SAM4SA16C"
16
17	config SOC_PART_NUMBER_SAM4S16B
18		bool "SAM4S16B"
19
20	config SOC_PART_NUMBER_SAM4S8C
21		bool "SAM4S8C"
22
23	config SOC_PART_NUMBER_SAM4S8B
24		bool "SAM4S8B"
25
26	config SOC_PART_NUMBER_SAM4S4C
27		bool "SAM4S4C"
28
29	config SOC_PART_NUMBER_SAM4S4B
30		bool "SAM4S4B"
31
32	config SOC_PART_NUMBER_SAM4S4A
33		bool "SAM4S4A"
34
35	config SOC_PART_NUMBER_SAM4S2C
36		bool "SAM4S2C"
37
38	config SOC_PART_NUMBER_SAM4S2B
39		bool "SAM4S2B"
40
41	config SOC_PART_NUMBER_SAM4S2A
42		bool "SAM4S2A"
43
44endchoice
45
46if SOC_SERIES_SAM4S
47
48config SOC_ATMEL_SAM4S_EXT_SLCK
49	bool "Atmel SAM4S to use external crystal oscillator for slow clock"
50	help
51	  Says y if you want to use external 32 kHz crystal
52	  oscillator to drive the slow clock. Note that this
53	  adds a few seconds to boot time, as the crystal
54	  needs to stabilize after power-up.
55
56	  Says n if you do not need accurate and precise timers.
57	  The slow clock will be driven by the internal fast
58	  RC oscillator running at 32 kHz.
59
60config SOC_ATMEL_SAM4S_EXT_MAINCK
61	bool "Atmel SAM4S to use external crystal oscillator for main clock"
62	help
63	  The main clock is being used to drive the PLL, and
64	  thus driving the processor clock.
65
66	  Says y if you want to use external crystal oscillator
67	  to drive the main clock. Note that this adds about
68	  a second to boot time, as the crystal needs to
69	  stabilize after power-up.
70
71	  The crystal used here can be from 3 to 20 MHz.
72
73	  Says n here will use the internal fast RC oscillator
74	  running at 12 MHz.
75
76config SOC_ATMEL_SAM4S_PLLA_MULA
77	hex "PLL MULA"
78	default 0x09
79	help
80	  This is the multiplier (MULA) used by the PLL.
81	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
82
83	  Board config file can override this settings
84	  for a particular board.
85
86	  With default of MULA == 9, and DIVA == 1,
87	  PLL is running at 10 times of main clock.
88
89config SOC_ATMEL_SAM4S_PLLA_DIVA
90	hex "PLL DIVA"
91	default 0x01
92	help
93	  This is the divider (DIVA) used by the PLL.
94	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
95
96	  Board config file can override this settings
97	  for a particular board.
98
99	  With default of MULA == 9, and DIVA == 1,
100	  PLL is running at 10 times of main clock.
101
102config SOC_ATMEL_SAM4S_WAIT_MODE
103	bool "Atmel SAM4S goes to Wait mode instead of Sleep mode"
104	depends on SOC_ATMEL_SAM4S_EXT_MAINCK
105	default y if DEBUG
106	help
107	  For JTAG debugging CPU clock (HCLK) should not stop. In order
108	  to achieve this, make CPU go to Wait mode instead of Sleep
109	  mode while using external crystal oscillator for main clock.
110
111endif # SOC_SERIES_SAM4S
112