1 /* 2 * Copyright 2022 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* 8 * SD card specification 9 */ 10 11 #ifndef ZEPHYR_SUBSYS_SD_SPEC_H_ 12 #define ZEPHYR_SUBSYS_SD_SPEC_H_ 13 14 #include <stdint.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /** 21 * @brief SD specification command opcodes 22 * 23 * SD specification command opcodes. Note that some command opcodes are 24 * specific to SDIO cards, or cards running in SPI mode instead of native SD 25 * mode. 26 */ 27 enum sd_opcode { 28 SD_GO_IDLE_STATE = 0, 29 MMC_SEND_OP_COND = 1, 30 SD_ALL_SEND_CID = 2, 31 SD_SEND_RELATIVE_ADDR = 3, 32 MMC_SEND_RELATIVE_ADDR = 3, 33 SDIO_SEND_OP_COND = 5, /* SDIO cards only */ 34 SD_SWITCH = 6, 35 SD_SELECT_CARD = 7, 36 SD_SEND_IF_COND = 8, 37 MMC_SEND_EXT_CSD = 8, 38 SD_SEND_CSD = 9, 39 SD_SEND_CID = 10, 40 SD_VOL_SWITCH = 11, 41 SD_STOP_TRANSMISSION = 12, 42 SD_SEND_STATUS = 13, 43 MMC_CHECK_BUS_TEST = 14, 44 SD_GO_INACTIVE_STATE = 15, 45 SD_SET_BLOCK_SIZE = 16, 46 SD_READ_SINGLE_BLOCK = 17, 47 SD_READ_MULTIPLE_BLOCK = 18, 48 SD_SEND_TUNING_BLOCK = 19, 49 MMC_SEND_BUS_TEST = 19, 50 MMC_SEND_TUNING_BLOCK = 21, 51 SD_SET_BLOCK_COUNT = 23, 52 SD_WRITE_SINGLE_BLOCK = 24, 53 SD_WRITE_MULTIPLE_BLOCK = 25, 54 SD_ERASE_BLOCK_START = 32, 55 SD_ERASE_BLOCK_END = 33, 56 SD_ERASE_BLOCK_OPERATION = 38, 57 SD_APP_CMD = 55, 58 SD_SPI_READ_OCR = 58, /* SPI mode only */ 59 SD_SPI_CRC_ON_OFF = 59, /* SPI mode only */ 60 }; 61 62 /** 63 * @brief SD application command opcodes. 64 * 65 * all application command opcodes must be prefixed with a CMD55 command 66 * to inform the SD card the next command is an application-specific one. 67 */ 68 enum sd_app_cmd { 69 SD_APP_SET_BUS_WIDTH = 6, 70 SD_APP_SEND_STATUS = 13, 71 SD_APP_SEND_NUM_WRITTEN_BLK = 22, 72 SD_APP_SET_WRITE_BLK_ERASE_CNT = 23, 73 SD_APP_SEND_OP_COND = 41, 74 SD_APP_CLEAR_CARD_DETECT = 42, 75 SD_APP_SEND_SCR = 51, 76 }; 77 78 /** 79 * @brief Native SD mode R1 response status flags 80 * 81 * Native response flags for SD R1 response, used to check for error in command. 82 */ 83 enum sd_r1_status { 84 /* Bits 0-2 reserved */ 85 SD_R1_AUTH_ERR = BIT(3), 86 /* Bit 4 reserved for SDIO */ 87 SD_R1_APP_CMD = BIT(5), 88 SD_R1_FX_EVENT = BIT(6), 89 /* Bit 7 reserved */ 90 SD_R1_RDY_DATA = BIT(8), 91 SD_R1_CUR_STATE = (0xFU << 9), 92 SD_R1_ERASE_RESET = BIT(13), 93 SD_R1_ECC_DISABLED = BIT(14), 94 SD_R1_ERASE_SKIP = BIT(15), 95 SD_R1_CSD_OVERWRITE = BIT(16), 96 /* Bits 17-18 reserved */ 97 SD_R1_ERR = BIT(19), 98 SD_R1_CC_ERR = BIT(20), 99 SD_R1_ECC_FAIL = BIT(21), 100 SD_R1_ILLEGAL_CMD = BIT(22), 101 SD_R1_CRC_ERR = BIT(23), 102 SD_R1_UNLOCK_FAIL = BIT(24), 103 SD_R1_CARD_LOCKED = BIT(25), 104 SD_R1_WP_VIOLATION = BIT(26), 105 SD_R1_ERASE_PARAM = BIT(27), 106 SD_R1_ERASE_SEQ_ERR = BIT(28), 107 SD_R1_BLOCK_LEN_ERR = BIT(29), 108 SD_R1_ADDR_ERR = BIT(30), 109 SD_R1_OUT_OF_RANGE = BIT(31), 110 SD_R1_ERR_FLAGS = (SD_R1_AUTH_ERR | 111 SD_R1_ERASE_SKIP | 112 SD_R1_CSD_OVERWRITE | 113 SD_R1_ERR | 114 SD_R1_CC_ERR | 115 SD_R1_ECC_FAIL | 116 SD_R1_ILLEGAL_CMD | 117 SD_R1_CRC_ERR | 118 SD_R1_UNLOCK_FAIL | 119 SD_R1_WP_VIOLATION | 120 SD_R1_ERASE_PARAM | 121 SD_R1_ERASE_SEQ_ERR | 122 SD_R1_BLOCK_LEN_ERR | 123 SD_R1_ADDR_ERR | 124 SD_R1_OUT_OF_RANGE), 125 SD_R1ERR_NONE = 0, 126 }; 127 128 #define SD_R1_CURRENT_STATE(x) (((x) & SD_R1_CUR_STATE) >> 9U) 129 130 /** 131 * @brief SD current state values 132 * 133 * SD current state values, contained in R1 response data. 134 */ 135 enum sd_r1_current_state { 136 SDMMC_R1_IDLE = 0U, 137 SDMMC_R1_READY = 1U, 138 SDMMC_R1_IDENTIFY = 2U, 139 SDMMC_R1_STANDBY = 3U, 140 SDMMC_R1_TRANSFER = 4U, 141 SDMMC_R1_SEND_DATA = 5U, 142 SDMMC_R1_RECIVE_DATA = 6U, 143 SDMMC_R1_PROGRAM = 7U, 144 SDMMC_R1_DISCONNECT = 8U, 145 }; 146 147 /** 148 * @brief SPI SD mode R1 response status flags 149 * 150 * SPI mode R1 response flags. Used to check for error in SD SPI mode command. 151 */ 152 enum sd_spi_r1_error_flag { 153 SD_SPI_R1PARAMETER_ERR = BIT(6), 154 SD_SPI_R1ADDRESS_ERR = BIT(5), 155 SD_SPI_R1ERASE_SEQ_ERR = BIT(4), 156 SD_SPI_R1CMD_CRC_ERR = BIT(3), 157 SD_SPI_R1ILLEGAL_CMD_ERR = BIT(2), 158 SD_SPI_R1ERASE_RESET = BIT(1), 159 SD_SPI_R1IDLE_STATE = BIT(0), 160 }; 161 162 /** 163 * @brief SPI SD mode R2 response status flags 164 * 165 * SPI mode R2 response flags. Sent in response to SEND_STATUS command. Used 166 * to check status of SD card. 167 */ 168 enum sd_spi_r2_status { 169 SDHC_SPI_R2_CARD_LOCKED = BIT(8), 170 SDHC_SPI_R2_UNLOCK_FAIL = BIT(9), 171 SDHC_SPI_R2_ERR = BIT(10), 172 SDHC_SPI_R2_CC_ERR = BIT(11), 173 SDHC_SPI_R2_ECC_FAIL = BIT(12), 174 SDHC_SPI_R2_WP_VIOLATION = BIT(13), 175 SDHC_SPI_R2_ERASE_PARAM = BIT(14), 176 SDHC_SPI_R2_OUT_OF_RANGE = BIT(15), 177 }; 178 179 /* Byte length of SD SPI mode command */ 180 #define SD_SPI_CMD_SIZE 6 181 #define SD_SPI_CMD_BODY_SIZE (SD_SPI_CMD_SIZE - 1) 182 /* Byte length of CRC16 appended to data blocks in SPI mode */ 183 #define SD_SPI_CRC16_SIZE 2 184 185 /* SPI Command flags */ 186 #define SD_SPI_START 0x80 187 #define SD_SPI_TX 0x40 188 #define SD_SPI_CMD 0x3F 189 190 /* SPI Data block tokens */ 191 #define SD_SPI_TOKEN_SINGLE 0xFE 192 #define SD_SPI_TOKEN_MULTI_WRITE 0xFC 193 #define SD_SPI_TOKEN_STOP_TRAN 0xFD 194 195 /* SPI Data block responses */ 196 #define SD_SPI_RESPONSE_ACCEPTED 0x05 197 #define SD_SPI_RESPONSE_CRC_ERR 0x0B 198 #define SD_SPI_RESPONSE_WRITE_ERR 0x0C 199 200 /* Masks used in SD interface condition query (CMD8) */ 201 #define SD_IF_COND_VHS_MASK (0x0F << 8) 202 #define SD_IF_COND_VHS_3V3 BIT(8) 203 #define SD_IF_COND_CHECK 0xAA 204 205 /** 206 * @brief SD response types 207 * 208 * SD response types. Note that SPI mode has difference response types than 209 * cards in native SD mode. 210 */ 211 enum sd_rsp_type { 212 /* Native response types (lower 4 bits) */ 213 SD_RSP_TYPE_NONE = 0U, 214 SD_RSP_TYPE_R1 = 1U, 215 SD_RSP_TYPE_R1b = 2U, 216 SD_RSP_TYPE_R2 = 3U, 217 SD_RSP_TYPE_R3 = 4U, 218 SD_RSP_TYPE_R4 = 5U, 219 SD_RSP_TYPE_R5 = 6U, 220 SD_RSP_TYPE_R5b = 7U, 221 SD_RSP_TYPE_R6 = 8U, 222 SD_RSP_TYPE_R7 = 9U, 223 /* SPI response types (bits [7:4]) */ 224 SD_SPI_RSP_TYPE_R1 = (1U << 4), 225 SD_SPI_RSP_TYPE_R1b = (2U << 4), 226 SD_SPI_RSP_TYPE_R2 = (3U << 4), 227 SD_SPI_RSP_TYPE_R3 = (4U << 4), 228 SD_SPI_RSP_TYPE_R4 = (5U << 4), 229 SD_SPI_RSP_TYPE_R5 = (6U << 4), 230 SD_SPI_RSP_TYPE_R7 = (7U << 4), 231 }; 232 233 /** 234 * @brief SD support flags 235 * 236 * flags used by SD subsystem to determine support for SD card features. 237 */ 238 enum sd_support_flag { 239 SD_HIGH_CAPACITY_FLAG = BIT(1), 240 SD_4BITS_WIDTH = BIT(2), 241 SD_SDHC_FLAG = BIT(3), 242 SD_SDXC_FLAG = BIT(4), 243 SD_1800MV_FLAG = BIT(5), 244 SD_3000MV_FLAG = BIT(6), 245 SD_CMD23_FLAG = BIT(7), 246 SD_SPEED_CLASS_CONTROL_FLAG = BIT(8), 247 }; 248 249 250 /** 251 * @brief SD OCR bit flags 252 * 253 * bit flags present in SD OCR response. Used to determine status and 254 * supported functions of SD card. 255 */ 256 enum sd_ocr_flag { 257 SD_OCR_PWR_BUSY_FLAG = BIT(31), 258 /*!< Power up busy status */ 259 SD_OCR_HOST_CAP_FLAG = BIT(30), 260 /*!< Card capacity status */ 261 SD_OCR_CARD_CAP_FLAG = SD_OCR_HOST_CAP_FLAG, 262 /*!< Card capacity status */ 263 SD_OCR_SWITCH_18_REQ_FLAG = BIT(24), 264 /*!< Switch to 1.8V request */ 265 SD_OCR_SWITCH_18_ACCEPT_FLAG = SD_OCR_SWITCH_18_REQ_FLAG, 266 /*!< Switch to 1.8V accepted */ 267 SD_OCR_VDD27_28FLAG = BIT(15), 268 /*!< VDD 2.7-2.8 */ 269 SD_OCR_VDD28_29FLAG = BIT(16), 270 /*!< VDD 2.8-2.9 */ 271 SD_OCR_VDD29_30FLAG = BIT(17), 272 /*!< VDD 2.9-3.0 */ 273 SD_OCR_VDD30_31FLAG = BIT(18), 274 /*!< VDD 2.9-3.0 */ 275 SD_OCR_VDD31_32FLAG = BIT(19), 276 /*!< VDD 3.0-3.1 */ 277 SD_OCR_VDD32_33FLAG = BIT(20), 278 /*!< VDD 3.1-3.2 */ 279 SD_OCR_VDD33_34FLAG = BIT(21), 280 /*!< VDD 3.2-3.3 */ 281 SD_OCR_VDD34_35FLAG = BIT(22), 282 /*!< VDD 3.3-3.4 */ 283 SD_OCR_VDD35_36FLAG = BIT(23), 284 /*!< VDD 3.4-3.5 */ 285 }; 286 287 /** 288 * @brief MMC OCR bit flags 289 * 290 * bit flags present in MMC OCR response. Used to determine status and 291 * supported functions of MMC card. 292 */ 293 enum mmc_ocr_flag { 294 MMC_OCR_VDD170_195FLAG = BIT(7), 295 MMC_OCR_VDD20_26FLAG = 0x7F << 8, 296 MMC_OCR_VDD27_36FLAG = 0x1FF << 15, 297 MMC_OCR_SECTOR_MODE = BIT(30), 298 MMC_OCR_PWR_BUSY_FLAG = BIT(31) 299 }; 300 301 #define SDIO_OCR_IO_NUMBER_SHIFT (28U) 302 /* Lower 24 bits hold SDIO I/O OCR */ 303 #define SDIO_IO_OCR_MASK (0xFFFFFFU) 304 305 /** 306 * @brief SDIO OCR bit flags 307 * 308 * bit flags present in SDIO OCR response. Used to determine status and 309 * supported functions of SDIO card. 310 */ 311 enum sdio_ocr_flag { 312 SDIO_OCR_IO_READY_FLAG = BIT(31), 313 SDIO_OCR_IO_NUMBER = (7U << 28U), /*!< Number of io function */ 314 SDIO_OCR_MEM_PRESENT_FLAG = BIT(27), /*!< Memory present flag */ 315 SDIO_OCR_180_VOL_FLAG = BIT(24), /*!< Switch to 1.8v signalling */ 316 SDIO_OCR_VDD20_21FLAG = BIT(8), /*!< VDD 2.0-2.1 */ 317 SDIO_OCR_VDD21_22FLAG = BIT(9), /*!< VDD 2.1-2.2 */ 318 SDIO_OCR_VDD22_23FLAG = BIT(10), /*!< VDD 2.2-2.3 */ 319 SDIO_OCR_VDD23_24FLAG = BIT(11), /*!< VDD 2.3-2.4 */ 320 SDIO_OCR_VDD24_25FLAG = BIT(12), /*!< VDD 2.4-2.5 */ 321 SDIO_OCR_VDD25_26FLAG = BIT(13), /*!< VDD 2.5-2.6 */ 322 SDIO_OCR_VDD26_27FLAG = BIT(14), /*!< VDD 2.6-2.7 */ 323 SDIO_OCR_VDD27_28FLAG = BIT(15), /*!< VDD 2.7-2.8 */ 324 SDIO_OCR_VDD28_29FLAG = BIT(16), /*!< VDD 2.8-2.9 */ 325 SDIO_OCR_VDD29_30FLAG = BIT(17), /*!< VDD 2.9-3.0 */ 326 SDIO_OCR_VDD30_31FLAG = BIT(18), /*!< VDD 2.9-3.0 */ 327 SDIO_OCR_VDD31_32FLAG = BIT(19), /*!< VDD 3.0-3.1 */ 328 SDIO_OCR_VDD32_33FLAG = BIT(20), /*!< VDD 3.1-3.2 */ 329 SDIO_OCR_VDD33_34FLAG = BIT(21), /*!< VDD 3.2-3.3 */ 330 SDIO_OCR_VDD34_35FLAG = BIT(22), /*!< VDD 3.3-3.4 */ 331 SDIO_OCR_VDD35_36FLAG = BIT(23), /*!< VDD 3.4-3.5 */ 332 }; 333 334 335 /** 336 * @brief SD switch arguments 337 * 338 * SD CMD6 can either check or set a function. Bitfields are used to indicate 339 * feature support when checking a function, and when setting a function an 340 * integer value is used to select it. 341 */ 342 enum sd_switch_arg { 343 SD_SWITCH_CHECK = 0U, 344 /*!< SD switch mode 0: check function */ 345 SD_SWITCH_SET = 1U, 346 /*!< SD switch mode 1: set function */ 347 }; 348 349 /** 350 * @brief SD switch group numbers 351 * 352 * SD CMD6 has multiple function groups it can check/set. These indicies are 353 * used to determine which group CMD6 will interact with. 354 */ 355 enum sd_group_num { 356 SD_GRP_TIMING_MODE = 0U, 357 /*!< access mode group*/ 358 SD_GRP_CMD_SYS_MODE = 1U, 359 /*!< command system group*/ 360 SD_GRP_DRIVER_STRENGTH_MODE = 2U, 361 /*!< driver strength group*/ 362 SD_GRP_CURRENT_LIMIT_MODE = 3U, 363 /*!< current limit group*/ 364 }; 365 366 /* Maximum data rate possible for SD high speed cards */ 367 enum hs_max_data_rate { 368 HS_MAX_DTR = 50000000, 369 }; 370 371 /** 372 * @brief SD bus speed support bit flags 373 * 374 * Bit flags indicating support for SD bus speeds. 375 * these bit flags are provided as a response to CMD6 by the card 376 */ 377 enum sd_bus_speed { 378 UHS_SDR12_BUS_SPEED = BIT(0), 379 HIGH_SPEED_BUS_SPEED = BIT(1), 380 UHS_SDR25_BUS_SPEED = BIT(1), 381 UHS_SDR50_BUS_SPEED = BIT(2), 382 UHS_SDR104_BUS_SPEED = BIT(3), 383 UHS_DDR50_BUS_SPEED = BIT(4), 384 }; 385 386 /** 387 * @brief SD timing mode function selection values. 388 * 389 * sent to the card via CMD6 to select a card speed, and used by SD host 390 * controller to identify timing of card. 391 */ 392 enum sd_timing_mode { 393 SD_TIMING_SDR12 = 0U, 394 /*!< Default mode & SDR12 */ 395 SD_TIMING_SDR25 = 1U, 396 /*!< High speed mode & SDR25 */ 397 SD_TIMING_SDR50 = 2U, 398 /*!< SDR50 mode*/ 399 SD_TIMING_SDR104 = 3U, 400 /*!< SDR104 mode */ 401 SD_TIMING_DDR50 = 4U, 402 /*!< DDR50 mode */ 403 }; 404 405 /** 406 * @brief SD host controller clock speed 407 * 408 * Controls the SD host controller clock speed on the SD bus. 409 */ 410 enum sdhc_clock_speed { 411 SDMMC_CLOCK_400KHZ = 400000U, 412 SD_CLOCK_25MHZ = 25000000U, 413 SD_CLOCK_50MHZ = 50000000U, 414 SD_CLOCK_100MHZ = 100000000U, 415 SD_CLOCK_208MHZ = 208000000U, 416 MMC_CLOCK_26MHZ = 26000000U, 417 MMC_CLOCK_52MHZ = 52000000U, 418 MMC_CLOCK_DDR52 = 52000000U, 419 MMC_CLOCK_HS200 = 200000000U, 420 MMC_CLOCK_HS400 = 200000000U, /* Same clock freq as HS200, just DDR */ 421 }; 422 423 /** 424 * @brief SD current setting values 425 * 426 * Used with CMD6 to inform the card what its maximum current draw is. 427 */ 428 enum sd_current_setting { 429 SD_SET_CURRENT_200MA = 0, 430 SD_SET_CURRENT_400MA = 1, 431 SD_SET_CURRENT_600MA = 2, 432 SD_SET_CURRENT_800MA = 3, 433 }; 434 435 /** 436 * @brief SD current support bitfield 437 * 438 * Used with CMD6 to determine the maximum current the card will draw. 439 */ 440 enum sd_current_limit { 441 SD_MAX_CURRENT_200MA = BIT(0), 442 /*!< default current limit */ 443 SD_MAX_CURRENT_400MA = BIT(1), 444 /*!< current limit to 400MA */ 445 SD_MAX_CURRENT_600MA = BIT(2), 446 /*!< current limit to 600MA */ 447 SD_MAX_CURRENT_800MA = BIT(3), 448 /*!< current limit to 800MA */ 449 }; 450 451 /** 452 * @brief SD driver types 453 * 454 * Used with CMD6 to determine the driver type the card should use. 455 */ 456 enum sd_driver_type { 457 SD_DRIVER_TYPE_B = 0x1, 458 SD_DRIVER_TYPE_A = 0x2, 459 SD_DRIVER_TYPE_C = 0x4, 460 SD_DRIVER_TYPE_D = 0x8, 461 }; 462 463 /** 464 * @brief SD switch drive type selection 465 * 466 * These values are used to select the preferred driver type for an SD card. 467 */ 468 enum sd_driver_strength { 469 SD_DRV_STRENGTH_TYPEB = 0U, 470 /*!< default driver strength*/ 471 SD_DRV_STRENGTH_TYPEA = 1U, 472 /*!< driver strength TYPE A */ 473 SD_DRV_STRENGTH_TYPEC = 2U, 474 /*!< driver strength TYPE C */ 475 SD_DRV_STRENGTH_TYPED = 3U, 476 /*!< driver strength TYPE D */ 477 }; 478 479 /** 480 * @brief SD switch capabilities 481 * 482 * records switch capabilities for SD card. These capabilities are set 483 * and queried via CMD6 484 */ 485 struct sd_switch_caps { 486 enum hs_max_data_rate hs_max_dtr; 487 enum sdhc_clock_speed uhs_max_dtr; 488 enum sd_bus_speed bus_speed; 489 enum sd_driver_type sd_drv_type; 490 enum sd_current_limit sd_current_limit; 491 }; 492 493 494 #define SD_PRODUCT_NAME_BYTES (5U) 495 496 /** 497 * @brief SD card identification register 498 * 499 * Layout of SD card identification register 500 */ 501 struct sd_cid { 502 uint8_t manufacturer; 503 /*!< Manufacturer ID [127:120] */ 504 uint16_t application; 505 /*!< OEM/Application ID [119:104] */ 506 uint8_t name[SD_PRODUCT_NAME_BYTES]; 507 /*!< Product name [103:64] */ 508 uint8_t version; 509 /*!< Product revision [63:56] */ 510 uint32_t ser_num; 511 /*!< Product serial number [55:24] */ 512 uint16_t date; 513 /*!< Manufacturing date [19:8] */ 514 }; 515 516 /** 517 * @brief SD card specific data register. 518 * 519 * Card specific data register. contains additional data about SD card. 520 */ 521 struct sd_csd { 522 uint8_t csd_structure; 523 /*!< CSD structure [127:126] */ 524 uint8_t read_time1; 525 /*!< Data read access-time-1 [119:112] */ 526 uint8_t read_time2; 527 /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ 528 uint8_t xfer_rate; 529 /*!< Maximum data transfer rate [103:96] */ 530 uint16_t cmd_class; 531 /*!< Card command classes [95:84] */ 532 uint8_t read_blk_len; 533 /*!< Maximum read data block length [83:80] */ 534 uint16_t flags; 535 /*!< Flags in _sd_csd_flag */ 536 uint32_t device_size; 537 /*!< Device size [73:62] */ 538 uint8_t read_current_min; 539 /*!< Maximum read current at VDD min [61:59] */ 540 uint8_t read_current_max; 541 /*!< Maximum read current at VDD max [58:56] */ 542 uint8_t write_current_min; 543 /*!< Maximum write current at VDD min [55:53] */ 544 uint8_t write_current_max; 545 /*!< Maximum write current at VDD max [52:50] */ 546 uint8_t dev_size_mul; 547 /*!< Device size multiplier [49:47] */ 548 uint8_t erase_size; 549 /*!< Erase sector size [45:39] */ 550 uint8_t write_prtect_size; 551 /*!< Write protect group size [38:32] */ 552 uint8_t write_speed_factor; 553 /*!< Write speed factor [28:26] */ 554 uint8_t write_blk_len; 555 /*!< Maximum write data block length [25:22] */ 556 uint8_t file_fmt; 557 /*!< File format [11:10] */ 558 }; 559 560 /** 561 * @brief MMC Maximum Frequency 562 * 563 * Max freq in MMC csd 564 */ 565 enum mmc_csd_freq { 566 MMC_MAXFREQ_100KHZ = 0U << 0U, 567 MMC_MAXFREQ_1MHZ = 1U << 0U, 568 MMC_MAXFREQ_10MHZ = 2U << 0U, 569 MMC_MAXFREQ_100MHZ = 3U << 0U, 570 MMC_MAXFREQ_MULT_10 = 1U << 3U, 571 MMC_MAXFREQ_MULT_12 = 2U << 3U, 572 MMC_MAXFREQ_MULT_13 = 3U << 3U, 573 MMC_MAXFREQ_MULT_15 = 4U << 3U, 574 MMC_MAXFREQ_MULT_20 = 5U << 3U, 575 MMC_MAXFREQ_MULT_26 = 6U << 3U, 576 MMC_MAXFREQ_MULT_30 = 7U << 3U, 577 MMC_MAXFREQ_MULT_35 = 8U << 3U, 578 MMC_MAXFREQ_MULT_40 = 9U << 3U, 579 MMC_MAXFREQ_MULT_45 = 0xAU << 3U, 580 MMC_MAXFREQ_MULT_52 = 0xBU << 3U, 581 MMC_MAXFREQ_MULT_55 = 0xCU << 3U, 582 MMC_MAXFREQ_MULT_60 = 0xDU << 3U, 583 MMC_MAXFREQ_MULT_70 = 0xEU << 3U, 584 MMC_MAXFREQ_MULT_80 = 0xFU << 3u 585 }; 586 587 /** 588 * @brief MMC Timing Modes 589 * 590 * MMC Timing Mode, encoded in EXT_CSD 591 */ 592 enum mmc_timing_mode { 593 MMC_LEGACY_TIMING = 0U, 594 MMC_HS_TIMING = 1U, 595 MMC_HS200_TIMING = 2U, 596 MMC_HS400_TIMING = 3U 597 }; 598 599 /** 600 * @brief MMC Driver Strengths 601 * 602 * Encoded in EXT_CSD 603 */ 604 enum mmc_driver_strengths { 605 mmc_driv_type0 = 0U, 606 mmc_driv_type1 = 1U, 607 mmc_driv_type2 = 2U, 608 mmc_driv_type3 = 3U, 609 mmc_driv_type4 = 4U 610 }; 611 612 613 /** 614 * @brief MMC Device Type 615 * 616 * Encoded in EXT_CSD 617 */ 618 struct mmc_device_type { 619 bool MMC_HS400_DDR_1200MV; 620 bool MMC_HS400_DDR_1800MV; 621 bool MMC_HS200_SDR_1200MV; 622 bool MMC_HS200_SDR_1800MV; 623 bool MMC_HS_DDR_1200MV; 624 bool MMC_HS_DDR_1800MV; 625 bool MMC_HS_52_DV; 626 bool MMC_HS_26_DV; 627 }; 628 629 /** 630 * @brief CSD Revision 631 * 632 * Value of CSD rev in EXT_CSD 633 */ 634 enum mmc_ext_csd_rev { 635 MMC_5_1 = 8U, 636 MMC_5_0 = 7U, 637 MMC_4_5 = 6U, 638 MMC_4_4 = 5U, 639 MMC_4_3 = 3U, 640 MMC_4_2 = 2U, 641 MMC_4_1 = 1U, 642 MMC_4_0 = 0U 643 }; 644 645 /** 646 * @brief MMC extended card specific data register 647 * 648 * Extended card specific data register. 649 * Contains additional additional data about MMC card. 650 */ 651 struct mmc_ext_csd { 652 uint32_t sec_count; 653 /*!< Sector Count [215:212] >*/ 654 uint8_t bus_width; 655 /*!< Bus Width Mode [183] >*/ 656 enum mmc_timing_mode hs_timing; 657 /*!< High Speed Timing Mode [185] >*/ 658 struct mmc_device_type device_type; 659 /*!< Device Type [196] >*/ 660 enum mmc_ext_csd_rev rev; 661 /*!< Extended CSD Revision [192] >*/ 662 uint8_t power_class; 663 /*!< Selected power class [187]>*/ 664 uint8_t mmc_driver_strengths; 665 /*!< Driver strengths [197] >*/ 666 uint8_t pwr_class_200MHZ_VCCQ195; 667 /*!< Power class information for HS200 at VCC!=1.95V [237] >*/ 668 uint8_t pwr_class_HS400; 669 /*!< Power class information for HS400 [253] >*/ 670 uint32_t cache_size; 671 /*!< Size of eMMC cache [252:249]>*/ 672 }; 673 674 /** 675 * @brief SD card specific data flags 676 * 677 * flags used in decoding the SD card specific data register 678 */ 679 enum sd_csd_flag { 680 SD_CSD_READ_BLK_PARTIAL_FLAG = BIT(0), 681 /*!< Partial blocks for read allowed [79:79] */ 682 SD_CSD_WRITE_BLK_MISALIGN_FLAG = BIT(1), 683 /*!< Write block misalignment [78:78] */ 684 SD_CSD_READ_BLK_MISALIGN_FLAG = BIT(2), 685 /*!< Read block misalignment [77:77] */ 686 SD_CSD_DSR_IMPLEMENTED_FLAG = BIT(3), 687 /*!< DSR implemented [76:76] */ 688 SD_CSD_ERASE_BLK_EN_FLAG = BIT(4), 689 /*!< Erase single block enabled [46:46] */ 690 SD_CSD_WRITE_PROTECT_GRP_EN_FLAG = BIT(5), 691 /*!< Write protect group enabled [31:31] */ 692 SD_CSD_WRITE_BLK_PARTIAL_FLAG = BIT(6), 693 /*!< Partial blocks for write allowed [21:21] */ 694 SD_CSD_FILE_FMT_GRP_FLAG = BIT(7), 695 /*!< File format group [15:15] */ 696 SD_CSD_COPY_FLAG = BIT(8), 697 /*!< Copy flag [14:14] */ 698 SD_CSD_PERMANENT_WRITE_PROTECT_FLAG = BIT(9), 699 /*!< Permanent write protection [13:13] */ 700 SD_CSD_TMP_WRITE_PROTECT_FLAG = BIT(10), 701 /*!< Temporary write protection [12:12] */ 702 }; 703 704 /** 705 * @brief SD card configuration register 706 * 707 * Even more SD card data. 708 */ 709 struct sd_scr { 710 uint8_t scr_structure; 711 /*!< SCR Structure [63:60] */ 712 uint8_t sd_spec; 713 /*!< SD memory card specification version [59:56] */ 714 uint16_t flags; 715 /*!< SCR flags in _sd_scr_flag */ 716 uint8_t sd_sec; 717 /*!< Security specification supported [54:52] */ 718 uint8_t sd_width; 719 /*!< Data bus widths supported [51:48] */ 720 uint8_t sd_ext_sec; 721 /*!< Extended security support [46:43] */ 722 uint8_t cmd_support; 723 /*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ 724 uint32_t rsvd; 725 /*!< reserved for manufacturer usage [31:0] */ 726 }; 727 728 /** 729 * @brief SD card configuration register 730 * 731 * flags used in decoding the SD card configuration register 732 */ 733 enum sd_scr_flag { 734 SD_SCR_DATA_STATUS_AFTER_ERASE = BIT(0), 735 /*!< Data status after erases [55:55] */ 736 SD_SCR_SPEC3 = BIT(1), 737 /*!< Specification version 3.00 or higher [47:47]*/ 738 }; 739 740 /** 741 * @brief SD specification version 742 * 743 * SD spec version flags used in decoding the SD card configuration register 744 */ 745 enum sd_spec_version { 746 SD_SPEC_VER1_0 = BIT(0), 747 /*!< SD card version 1.0-1.01 */ 748 SD_SPEC_VER1_1 = BIT(1), 749 /*!< SD card version 1.10 */ 750 SD_SPEC_VER2_0 = BIT(2), 751 /*!< SD card version 2.00 */ 752 SD_SPEC_VER3_0 = BIT(3), 753 /*!< SD card version 3.0 */ 754 }; 755 756 757 #define SDMMC_DEFAULT_BLOCK_SIZE (512U) 758 #define MMC_EXT_CSD_BYTES 512 759 760 #ifdef __cplusplus 761 } 762 #endif 763 764 #endif /* ZEPHYR_SUBSYS_SD_SPEC_H_ */ 765
