1 /*
2  * Copyright (c) 2021 IoT.bzh
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_
9 
10 /**
11  * @brief Utility macro to build IPSR property entry.
12  * IPSR: Peripheral Function Select Register
13  * Each IPSR bank can hold 8 cellules of 4 bits coded function.
14  *
15  * @param bank the IPSR register bank.
16  * @param shift the bit shift for this alternate function.
17  * @param func the 4 bits encoded alternate function.
18  *
19  * Function code    [ 0 : 3 ]
20  * Function shift   [ 4 : 9 ]
21  * IPSR bank        [ 10 : 13 ]
22  */
23 #define IPSR(bank, shift, func) (((bank) << 10U) | ((shift) << 4U) | (func))
24 
25 /* Arbitrary number to encode non capable gpio pin */
26 #define PIN_NOGPSR_START 1024U
27 
28 /**
29  * @brief Utility macro to encode a GPIO capable pin
30  *
31  * @param bank the GPIO bank
32  * @param pin the pin within the GPIO bank (0..31)
33  */
34 #define RCAR_GP_PIN(bank, pin)     (((bank) * 32U) + (pin))
35 
36 /**
37  * @brief Utility macro to encode a non capable GPIO pin
38  *
39  * @param pin the encoded pin number
40  */
41 #define RCAR_NOGP_PIN(pin)         (PIN_NOGPSR_START + pin)
42 
43 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_ */
44