1 /* 2 * Copyright 2021 Carlo Caione <ccaione@baylibre.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * Public APIs for external cache controller drivers 10 */ 11 12 #ifndef ZEPHYR_INCLUDE_DRIVERS_CACHE_H_ 13 #define ZEPHYR_INCLUDE_DRIVERS_CACHE_H_ 14 15 #include <stddef.h> 16 17 /** 18 * @brief External Cache Controller Interface 19 * @defgroup cache_external_interface External Cache Controller Interface 20 * @ingroup io_interfaces 21 * @{ 22 */ 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #if defined(CONFIG_DCACHE) 29 30 /** 31 * @brief Enable the d-cache 32 * 33 * Enable the data cache. 34 */ 35 void cache_data_enable(void); 36 37 /** 38 * @brief Disable the d-cache 39 * 40 * Disable the data cache. 41 */ 42 void cache_data_disable(void); 43 44 /** 45 * @brief Flush the d-cache 46 * 47 * Flush the whole data cache. 48 * 49 * @retval 0 If succeeded. 50 * @retval -ENOTSUP If not supported. 51 * @retval -errno Negative errno for other failures. 52 */ 53 int cache_data_flush_all(void); 54 55 /** 56 * @brief Invalidate the d-cache 57 * 58 * Invalidate the whole data cache. 59 * 60 * @retval 0 If succeeded. 61 * @retval -ENOTSUP If not supported. 62 * @retval -errno Negative errno for other failures. 63 */ 64 int cache_data_invd_all(void); 65 66 /** 67 * @brief Flush and Invalidate the d-cache 68 * 69 * Flush and Invalidate the whole data cache. 70 * 71 * @retval 0 If succeeded. 72 * @retval -ENOTSUP If not supported. 73 * @retval -errno Negative errno for other failures. 74 */ 75 int cache_data_flush_and_invd_all(void); 76 77 /** 78 * @brief Flush an address range in the d-cache 79 * 80 * Flush the specified address range of the data cache. 81 * 82 * @param addr Starting address to flush. 83 * @param size Range size. 84 * 85 * @retval 0 If succeeded. 86 * @retval -ENOTSUP If not supported. 87 * @retval -errno Negative errno for other failures. 88 */ 89 int cache_data_flush_range(void *addr, size_t size); 90 91 /** 92 * @brief Invalidate an address range in the d-cache 93 * 94 * Invalidate the specified address range of the data cache. 95 * 96 * @param addr Starting address to invalidate. 97 * @param size Range size. 98 * 99 * @retval 0 If succeeded. 100 * @retval -ENOTSUP If not supported. 101 * @retval -errno Negative errno for other failures. 102 */ 103 int cache_data_invd_range(void *addr, size_t size); 104 105 /** 106 * @brief Flush and Invalidate an address range in the d-cache 107 * 108 * Flush and Invalidate the specified address range of the data cache. 109 * 110 * @param addr Starting address to flush and invalidate. 111 * @param size Range size. 112 * 113 * @retval 0 If succeeded. 114 * @retval -ENOTSUP If not supported. 115 * @retval -errno Negative errno for other failures. 116 */ 117 int cache_data_flush_and_invd_range(void *addr, size_t size); 118 119 #if defined(CONFIG_DCACHE_LINE_SIZE_DETECT) 120 /** 121 * 122 * @brief Get the d-cache line size. 123 * 124 * The API is provided to dynamically detect the data cache line size at run 125 * time. 126 * 127 * The function must be implemented only when CONFIG_DCACHE_LINE_SIZE_DETECT is 128 * defined. 129 * 130 * @retval size Size of the d-cache line. 131 * @retval 0 If the d-cache is not enabled. 132 */ 133 size_t cache_data_line_size_get(void); 134 135 #endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */ 136 137 #endif /* CONFIG_DCACHE */ 138 139 #if defined(CONFIG_ICACHE) 140 141 /** 142 * @brief Enable the i-cache 143 * 144 * Enable the instruction cache. 145 */ 146 void cache_instr_enable(void); 147 148 /** 149 * @brief Disable the i-cache 150 * 151 * Disable the instruction cache. 152 */ 153 void cache_instr_disable(void); 154 155 /** 156 * @brief Flush the i-cache 157 * 158 * Flush the whole instruction cache. 159 * 160 * @retval 0 If succeeded. 161 * @retval -ENOTSUP If not supported. 162 * @retval -errno Negative errno for other failures. 163 */ 164 int cache_instr_flush_all(void); 165 166 /** 167 * @brief Invalidate the i-cache 168 * 169 * Invalidate the whole instruction cache. 170 * 171 * @retval 0 If succeeded. 172 * @retval -ENOTSUP If not supported. 173 * @retval -errno Negative errno for other failures. 174 */ 175 int cache_instr_invd_all(void); 176 177 /** 178 * @brief Flush and Invalidate the i-cache 179 * 180 * Flush and Invalidate the whole instruction cache. 181 * 182 * @retval 0 If succeeded. 183 * @retval -ENOTSUP If not supported. 184 * @retval -errno Negative errno for other failures. 185 */ 186 int cache_instr_flush_and_invd_all(void); 187 188 /** 189 * @brief Flush an address range in the i-cache 190 * 191 * Flush the specified address range of the instruction cache. 192 * 193 * @param addr Starting address to flush. 194 * @param size Range size. 195 * 196 * @retval 0 If succeeded. 197 * @retval -ENOTSUP If not supported. 198 * @retval -errno Negative errno for other failures. 199 */ 200 int cache_instr_flush_range(void *addr, size_t size); 201 202 /** 203 * @brief Invalidate an address range in the i-cache 204 * 205 * Invalidate the specified address range of the instruction cache. 206 * 207 * @param addr Starting address to invalidate. 208 * @param size Range size. 209 * 210 * @retval 0 If succeeded. 211 * @retval -ENOTSUP If not supported. 212 * @retval -errno Negative errno for other failures. 213 */ 214 int cache_instr_invd_range(void *addr, size_t size); 215 216 /** 217 * @brief Flush and Invalidate an address range in the i-cache 218 * 219 * Flush and Invalidate the specified address range of the instruction cache. 220 * 221 * @param addr Starting address to flush and invalidate. 222 * @param size Range size. 223 * 224 * @retval 0 If succeeded. 225 * @retval -ENOTSUP If not supported. 226 * @retval -errno Negative errno for other failures. 227 */ 228 int cache_instr_flush_and_invd_range(void *addr, size_t size); 229 230 #ifdef CONFIG_ICACHE_LINE_SIZE_DETECT 231 /** 232 * 233 * @brief Get the i-cache line size. 234 * 235 * The API is provided to dynamically detect the instruction cache line size at 236 * run time. 237 * 238 * The function must be implemented only when CONFIG_ICACHE_LINE_SIZE_DETECT is 239 * defined. 240 * 241 * @retval size Size of the d-cache line. 242 * @retval 0 If the d-cache is not enabled. 243 */ 244 size_t cache_instr_line_size_get(void); 245 246 #endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */ 247 248 #endif /* CONFIG_ICACHE */ 249 250 #ifdef __cplusplus 251 } 252 #endif 253 254 /** 255 * @} 256 */ 257 258 #endif /* ZEPHYR_INCLUDE_DRIVERS_CACHE_H_ */ 259
