1/* 2 * Copyright (c) 2022 Intel Corporation. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6#include "skeleton.dtsi" 7#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h> 8#include <zephyr/dt-bindings/i2c/i2c.h> 9#include <zephyr/dt-bindings/pcie/pcie.h> 10#include <zephyr/dt-bindings/gpio/gpio.h> 11 12/ { 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "intel,raptor-lake"; 20 d-cache-line-size = <64>; 21 reg = <0>; 22 }; 23 24 }; 25 26 dram0: memory@0 { 27 device_type = "memory"; 28 reg = <0x0 DT_DRAM_SIZE>; 29 }; 30 31 intc: ioapic@fec00000 { 32 compatible = "intel,ioapic"; 33 reg = <0xfec00000 0x1000>; 34 interrupt-controller; 35 #interrupt-cells = <3>; 36 }; 37 38 pcie0: pcie0 { 39 #address-cells = <1>; 40 #size-cells = <1>; 41 compatible = "intel,pcie"; 42 ranges; 43 44 smbus0: smbus0 { 45 compatible = "intel,pch-smbus"; 46 #address-cells = <1>; 47 #size-cells = <0>; 48 vendor-id = <0x8086>; 49 device-id = <0x7a23>; 50 interrupts = <18 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 51 interrupt-parent = <&intc>; 52 53 status = "okay"; 54 }; 55 56 i2c0: i2c0 { 57 compatible = "snps,designware-i2c"; 58 clock-frequency = <I2C_BITRATE_STANDARD>; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 vendor-id = <0x8086>; 62 device-id = <0x7acc>; 63 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 64 interrupt-parent = <&intc>; 65 66 status = "okay"; 67 }; 68 69 i2c1: i2c1 { 70 compatible = "snps,designware-i2c"; 71 clock-frequency = <I2C_BITRATE_STANDARD>; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 vendor-id = <0x8086>; 75 device-id = <0x7acd>; 76 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 77 interrupt-parent = <&intc>; 78 79 status = "okay"; 80 }; 81 82 i2c2: i2c2 { 83 compatible = "snps,designware-i2c"; 84 clock-frequency = <I2C_BITRATE_STANDARD>; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 vendor-id = <0x8086>; 88 device-id = <0x7ace>; 89 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 90 interrupt-parent = <&intc>; 91 92 status = "okay"; 93 }; 94 95 i2c3: i2c3 { 96 compatible = "snps,designware-i2c"; 97 clock-frequency = <I2C_BITRATE_STANDARD>; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 vendor-id = <0x8086>; 101 device-id = <0x7acf>; 102 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 103 interrupt-parent = <&intc>; 104 105 status = "disabled"; 106 }; 107 108 i2c4: i2c4 { 109 compatible = "snps,designware-i2c"; 110 clock-frequency = <I2C_BITRATE_STANDARD>; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 vendor-id = <0x8086>; 114 device-id = <0x7afc>; 115 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 116 interrupt-parent = <&intc>; 117 118 status = "disabled"; 119 }; 120 121 i2c5: i2c5 { 122 compatible = "snps,designware-i2c"; 123 clock-frequency = <I2C_BITRATE_STANDARD>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 vendor-id = <0x8086>; 127 device-id = <0x7afd>; 128 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 129 interrupt-parent = <&intc>; 130 131 status = "disabled"; 132 }; 133 134 i2c6: i2c6 { 135 compatible = "snps,designware-i2c"; 136 clock-frequency = <I2C_BITRATE_STANDARD>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 vendor-id = <0x8086>; 140 device-id = <0x7ada>; 141 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 142 interrupt-parent = <&intc>; 143 144 status = "disabled"; 145 }; 146 147 i2c7: i2c7 { 148 compatible = "snps,designware-i2c"; 149 clock-frequency = <I2C_BITRATE_STANDARD>; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 vendor-id = <0x8086>; 153 device-id = <0x7adb>; 154 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 155 interrupt-parent = <&intc>; 156 157 status = "disabled"; 158 }; 159 160 spi0: spi0 { 161 compatible = "intel,penwell-spi"; 162 vendor-id = <0x8086>; 163 device-id = <0x7aaa>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 pw,cs-mode = <0>; 167 pw,cs-output = <0>; 168 pw,fifo-depth = <64>; 169 cs-gpios = <&gpio_0_i 15 GPIO_ACTIVE_LOW>; 170 clock-frequency = <100000000>; 171 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 172 interrupt-parent = <&intc>; 173 status = "okay"; 174 }; 175 176 spi1: spi1 { 177 compatible = "intel,penwell-spi"; 178 vendor-id = <0x8086>; 179 device-id = <0x7aab>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 pw,cs-mode = <0>; 183 pw,cs-output = <0>; 184 pw,fifo-depth = <64>; 185 cs-gpios = <&gpio_0_i 19 GPIO_ACTIVE_LOW>; 186 clock-frequency = <100000000>; 187 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 188 interrupt-parent = <&intc>; 189 status = "disabled"; 190 }; 191 192 spi2: spi2 { 193 compatible = "intel,penwell-spi"; 194 vendor-id = <0x8086>; 195 device-id = <0x7afb>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 pw,cs-mode = <0>; 199 pw,cs-output = <0>; 200 pw,fifo-depth = <64>; 201 cs-gpios = <&gpio_0_r 12 GPIO_ACTIVE_LOW>; 202 clock-frequency = <100000000>; 203 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 204 interrupt-parent = <&intc>; 205 status = "disabled"; 206 }; 207 208 uart0: uart0 { 209 compatible = "ns16550"; 210 vendor-id = <0x8086>; 211 device-id = <0x7aa8>; 212 reg-shift = <2>; 213 clock-frequency = <1843200>; 214 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 215 interrupt-parent = <&intc>; 216 current-speed = <115200>; 217 status = "okay"; 218 }; 219 220 uart1: uart1 { 221 compatible = "ns16550"; 222 vendor-id = <0x8086>; 223 device-id = <0x7aa9>; 224 reg-shift = <2>; 225 clock-frequency = <1843200>; 226 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 227 interrupt-parent = <&intc>; 228 current-speed = <115200>; 229 status = "okay"; 230 }; 231 232 uart2: uart2 { 233 compatible = "ns16550"; 234 vendor-id = <0x8086>; 235 device-id = <0x7afe>; 236 reg-shift = <2>; 237 clock-frequency = <1843200>; 238 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 239 interrupt-parent = <&intc>; 240 current-speed = <115200>; 241 status = "disabled"; 242 }; 243 244 uart3: uart3 { 245 compatible = "ns16550"; 246 vendor-id = <0x8086>; 247 device-id = <0x7adc>; 248 reg-shift = <2>; 249 clock-frequency = <1843200>; 250 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 251 interrupt-parent = <&intc>; 252 current-speed = <115200>; 253 status = "disabled"; 254 }; 255 256 uart4: uart4 { 257 compatible = "ns16550"; 258 vendor-id = <0x8086>; 259 device-id = <0x7add>; 260 reg-shift = <2>; 261 clock-frequency = <1843200>; 262 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 263 interrupt-parent = <&intc>; 264 current-speed = <115200>; 265 status = "disabled"; 266 }; 267 268 uart5: uart5 { 269 compatible = "ns16550"; 270 vendor-id = <0x8086>; 271 device-id = <0x7ade>; 272 reg-shift = <2>; 273 clock-frequency = <1843200>; 274 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 275 interrupt-parent = <&intc>; 276 current-speed = <115200>; 277 status = "disabled"; 278 }; 279 280 uart6: uart6 { 281 compatible = "ns16550"; 282 vendor-id = <0x8086>; 283 device-id = <0x7adf>; 284 reg-shift = <2>; 285 clock-frequency = <1843200>; 286 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 287 interrupt-parent = <&intc>; 288 current-speed = <115200>; 289 status = "disabled"; 290 }; 291 }; 292 293 soc { 294 #address-cells = <1>; 295 #size-cells = <1>; 296 compatible = "simple-bus"; 297 ranges; 298 299 vtd: vtd@fed91000 { 300 compatible = "intel,vt-d"; 301 reg = <0xfed91000 0x1000>; 302 303 status = "okay"; 304 }; 305 306 uart_ec_0: uart@3f8 { 307 compatible = "ns16550"; 308 reg = <0x000003f8 0x100>; 309 clock-frequency = <1843200>; 310 interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 311 interrupt-parent = <&intc>; 312 reg-shift = <0>; 313 io-mapped; 314 status = "okay"; 315 }; 316 317 gpio_0_i: gpio@e06e0700 { 318 compatible = "intel,gpio"; 319 reg = <0xe06e0700 0x1000>; 320 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 321 interrupt-parent = <&intc>; 322 group-index = <0x0>; 323 gpio-controller; 324 #gpio-cells = <2>; 325 ngpios = <23>; 326 pin-offset = <0>; 327 328 status = "okay"; 329 }; 330 331 gpio_0_r: gpio@e06e0890 { 332 compatible = "intel,gpio"; 333 reg = <0xe06e0890 0x1000>; 334 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 335 interrupt-parent = <&intc>; 336 group-index = <0x1>; 337 gpio-controller; 338 #gpio-cells = <2>; 339 ngpios = <22>; 340 pin-offset = <26>; 341 342 status = "okay"; 343 }; 344 345 gpio_0_j: gpio@e06e0a00 { 346 compatible = "intel,gpio"; 347 reg = <0xe06e0a00 0x1000>; 348 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 349 interrupt-parent = <&intc>; 350 group-index = <0x2>; 351 gpio-controller; 352 #gpio-cells = <2>; 353 ngpios = <12>; 354 pin-offset = <49>; 355 356 status = "okay"; 357 }; 358 359 gpio_1_b: gpio@e06d0700 { 360 compatible = "intel,gpio"; 361 reg = <0xe06d0700 0x1000>; 362 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 363 interrupt-parent = <&intc>; 364 group-index = <0x0>; 365 gpio-controller; 366 #gpio-cells = <2>; 367 ngpios = <24>; 368 pin-offset = <0>; 369 370 status = "okay"; 371 }; 372 373 gpio_1_g: gpio@e06d0880 { 374 compatible = "intel,gpio"; 375 reg = <0xe06d0880 0x1000>; 376 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 377 interrupt-parent = <&intc>; 378 group-index = <0x1>; 379 gpio-controller; 380 #gpio-cells = <2>; 381 ngpios = <8>; 382 pin-offset = <24>; 383 384 status = "okay"; 385 }; 386 387 gpio_1_h: gpio@e06d0900 { 388 compatible = "intel,gpio"; 389 reg = <0xe06d0900 0x1000>; 390 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 391 interrupt-parent = <&intc>; 392 group-index = <0x2>; 393 gpio-controller; 394 #gpio-cells = <2>; 395 ngpios = <24>; 396 pin-offset = <32>; 397 398 status = "okay"; 399 }; 400 401 gpio_3_a: gpio@e06b0790 { 402 compatible = "intel,gpio"; 403 reg = <0xe06b0790 0x1000>; 404 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 405 interrupt-parent = <&intc>; 406 group-index = <0x1>; 407 gpio-controller; 408 #gpio-cells = <2>; 409 ngpios = <15>; 410 pin-offset = <9>; 411 412 status = "okay"; 413 }; 414 415 gpio_3_c: gpio@e06b0890 { 416 compatible = "intel,gpio"; 417 reg = <0xe06b0890 0x1000>; 418 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 419 interrupt-parent = <&intc>; 420 group-index = <0x2>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 ngpios = <24>; 424 pin-offset = <25>; 425 426 status = "okay"; 427 }; 428 429 gpio_4_s: gpio@e06a0700 { 430 compatible = "intel,gpio"; 431 reg = <0xe06a0700 0x1000>; 432 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 433 interrupt-parent = <&intc>; 434 group-index = <0x0>; 435 gpio-controller; 436 #gpio-cells = <2>; 437 ngpios = <8>; 438 pin-offset = <0>; 439 440 status = "okay"; 441 }; 442 443 gpio_4_e: gpio@e06a0780 { 444 compatible = "intel,gpio"; 445 reg = <0xe06a0780 0x1000>; 446 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 447 interrupt-parent = <&intc>; 448 group-index = <0x1>; 449 gpio-controller; 450 #gpio-cells = <2>; 451 ngpios = <22>; 452 pin-offset = <8>; 453 454 status = "okay"; 455 }; 456 457 gpio_4_k: gpio@e06a08f0 { 458 compatible = "intel,gpio"; 459 reg = <0xe06a08f0 0x1000>; 460 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 461 interrupt-parent = <&intc>; 462 group-index = <0x2>; 463 gpio-controller; 464 #gpio-cells = <2>; 465 ngpios = <12>; 466 pin-offset = <25>; 467 468 status = "okay"; 469 }; 470 471 gpio_4_f: gpio@e06a09e0 { 472 compatible = "intel,gpio"; 473 reg = <0xe06a09e0 0x1000>; 474 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 475 interrupt-parent = <&intc>; 476 group-index = <0x3>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 ngpios = <24>; 480 pin-offset = <41>; 481 482 status = "okay"; 483 }; 484 485 gpio_5_d: gpio@e0690700 { 486 compatible = "intel,gpio"; 487 reg = <0xe0690700 0x1000>; 488 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 489 interrupt-parent = <&intc>; 490 group-index = <0x0>; 491 gpio-controller; 492 #gpio-cells = <2>; 493 ngpios = <24>; 494 pin-offset = <0>; 495 496 status = "okay"; 497 }; 498 499 rtc: counter: rtc@70 { 500 compatible = "motorola,mc146818"; 501 reg = <0x70 0x0D 0x71 0x0D>; 502 interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 503 interrupt-parent = <&intc>; 504 alarms-count = <1>; 505 506 status = "okay"; 507 }; 508 509 hpet: hpet@fed00000 { 510 compatible = "intel,hpet"; 511 reg = <0xfed00000 0x400>; 512 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; 513 interrupt-parent = <&intc>; 514 515 status = "okay"; 516 }; 517 518 tco_wdt: tco_wdt@400 { 519 compatible = "intel,tco-wdt"; 520 reg = <0x0400 0x20>; 521 }; 522 }; 523}; 524
