1/*
2 * Copyright (c) 2017 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			device_type = "cpu";
17			compatible = "intel,x86";
18			d-cache-line-size = <64>;
19			reg = <0>;
20		};
21
22	};
23
24	intc: ioapic@fec00000  {
25		compatible = "intel,ioapic";
26		reg = <0xfec00000 0x1000>;
27		interrupt-controller;
28		#interrupt-cells = <3>;
29	};
30
31	dram0: memory@0 {
32		device_type = "memory";
33		reg = <DT_DRAM_BASE DT_DRAM_SIZE>;
34	};
35
36	soc {
37		#address-cells = <1>;
38		#size-cells = <1>;
39		compatible = "simple-bus";
40		ranges;
41
42		uart0: uart@3f8 {
43			compatible = "ns16550";
44			reg = <0x000003f8 0x100>;
45			clock-frequency = <1843200>;
46			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
47			interrupt-parent = <&intc>;
48			reg-shift = <0>;
49			status = "disabled";
50		};
51
52		uart1: uart@2f8 {
53			compatible = "ns16550";
54			reg = <0x000002f8 0x100>;
55			clock-frequency = <1843200>;
56			interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
57			interrupt-parent = <&intc>;
58			reg-shift = <0>;
59			status = "disabled";
60		};
61
62		hpet: hpet@fed00000 {
63			compatible = "intel,hpet";
64			reg = <0xfed00000 0x400>;
65			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
66			interrupt-parent = <&intc>;
67
68			status = "disabled";
69		};
70
71		rtc: counter: rtc@70 {
72			compatible = "motorola,mc146818";
73			reg = <0x70 0x0D 0x71 0x0D>;
74			interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
75			interrupt-parent = <&intc>;
76			alarms-count = <1>;
77
78			status = "okay";
79		};
80
81	};
82};
83