1/* 2 * Copyright (c) 2020 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include "skeleton.dtsi" 8#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h> 9#include <zephyr/dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/pcie/pcie.h> 11 12/ { 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "intel,elkhart_lake"; 20 d-cache-line-size = <64>; 21 reg = <0>; 22 }; 23 24 }; 25 26 dram0: memory@0 { 27 device_type = "memory"; 28 reg = <0x0 DT_DRAM_SIZE>; 29 }; 30 31 ibecc: ibecc { 32 compatible = "intel,ibecc"; 33 status = "okay"; 34 }; 35 36 intc: ioapic@fec00000 { 37 compatible = "intel,ioapic"; 38 reg = <0xfec00000 0x1000>; 39 interrupt-controller; 40 #interrupt-cells = <3>; 41 }; 42 43 pcie0: pcie0 { 44 #address-cells = <1>; 45 #size-cells = <1>; 46 compatible = "intel,pcie"; 47 ranges; 48 49 ptm_root0: ptm_root0 { 50 compatible = "ptm-root"; 51 52 vendor-id = <0x8086>; 53 device-id = <0x4b38>; 54 55 status = "okay"; 56 }; 57 58 uart0: uart0 { 59 compatible = "ns16550"; 60 61 vendor-id = <0x8086>; 62 device-id = <0x4b28>; 63 64 reg-shift = <2>; 65 clock-frequency = <1843200>; 66 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 67 interrupt-parent = <&intc>; 68 status = "okay"; 69 current-speed = <115200>; 70 }; 71 72 uart1: uart1 { 73 compatible = "ns16550"; 74 75 vendor-id = <0x8086>; 76 device-id = <0x4b29>; 77 78 reg-shift = <2>; 79 clock-frequency = <1843200>; 80 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 81 interrupt-parent = <&intc>; 82 83 status = "okay"; 84 current-speed = <115200>; 85 }; 86 87 uart2: uart2 { 88 compatible = "ns16550"; 89 90 vendor-id = <0x8086>; 91 device-id = <0x4b4d>; 92 93 reg-shift = <2>; 94 clock-frequency = <1843200>; 95 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 96 interrupt-parent = <&intc>; 97 98 status = "okay"; 99 current-speed = <115200>; 100 }; 101 102 uart_pse_0: uart_pse_0 { 103 compatible = "ns16550"; 104 105 vendor-id = <0x8086>; 106 device-id = <0x4b96>; 107 108 reg-shift = <2>; 109 clock-frequency = <1843200>; 110 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 111 interrupt-parent = <&intc>; 112 113 status = "disabled"; 114 current-speed = <115200>; 115 }; 116 117 uart_pse_1: uart_pse_1 { 118 compatible = "ns16550"; 119 120 vendor-id = <0x8086>; 121 device-id = <0x4b97>; 122 123 reg-shift = <2>; 124 clock-frequency = <1843200>; 125 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 126 interrupt-parent = <&intc>; 127 128 status = "disabled"; 129 current-speed = <115200>; 130 }; 131 132 uart_pse_2: uart_pse_2 { 133 compatible = "ns16550"; 134 135 vendor-id = <0x8086>; 136 device-id = <0x4b98>; 137 138 reg-shift = <2>; 139 clock-frequency = <1843200>; 140 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 141 interrupt-parent = <&intc>; 142 143 status = "disabled"; 144 current-speed = <115200>; 145 }; 146 147 uart_pse_3: uart_pse_3 { 148 compatible = "ns16550"; 149 150 vendor-id = <0x8086>; 151 device-id = <0x4b99>; 152 153 reg-shift = <2>; 154 clock-frequency = <1843200>; 155 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 156 interrupt-parent = <&intc>; 157 158 status = "disabled"; 159 current-speed = <115200>; 160 }; 161 162 uart_pse_4: uart_pse_4 { 163 compatible = "ns16550"; 164 165 vendor-id = <0x8086>; 166 device-id = <0x4b9a>; 167 168 reg-shift = <2>; 169 clock-frequency = <1843200>; 170 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 171 interrupt-parent = <&intc>; 172 173 status = "disabled"; 174 current-speed = <115200>; 175 }; 176 177 uart_pse_5: uart_pse_5 { 178 compatible = "ns16550"; 179 180 vendor-id = <0x8086>; 181 device-id = <0x4b9b>; 182 183 reg-shift = <2>; 184 clock-frequency = <1843200>; 185 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 186 interrupt-parent = <&intc>; 187 188 status = "disabled"; 189 current-speed = <115200>; 190 }; 191 192 smbus0: smbus0 { 193 compatible = "intel,pch-smbus"; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 vendor-id = <0x8086>; 197 device-id = <0x4b23>; 198 interrupts = <16 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 199 interrupt-parent = <&intc>; 200 201 status = "okay"; 202 }; 203 204 i2c0: i2c0 { 205 compatible = "snps,designware-i2c"; 206 clock-frequency = <I2C_BITRATE_STANDARD>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 vendor-id = <0x8086>; 210 device-id = <0x4b78>; 211 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 212 interrupt-parent = <&intc>; 213 214 status = "okay"; 215 }; 216 217 i2c1: i2c1 { 218 compatible = "snps,designware-i2c"; 219 clock-frequency = <I2C_BITRATE_STANDARD>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 vendor-id = <0x8086>; 223 device-id = <0x4b79>; 224 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 225 interrupt-parent = <&intc>; 226 227 status = "okay"; 228 }; 229 230 i2c2: i2c2 { 231 compatible = "snps,designware-i2c"; 232 clock-frequency = <I2C_BITRATE_STANDARD>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 vendor-id = <0x8086>; 236 device-id = <0x4b7a>; 237 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 238 interrupt-parent = <&intc>; 239 240 status = "okay"; 241 }; 242 243 i2c3: i2c3 { 244 compatible = "snps,designware-i2c"; 245 clock-frequency = <I2C_BITRATE_STANDARD>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 vendor-id = <0x8086>; 249 device-id = <0x4b7b>; 250 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 251 interrupt-parent = <&intc>; 252 253 status = "okay"; 254 }; 255 256 i2c4: i2c4 { 257 compatible = "snps,designware-i2c"; 258 clock-frequency = <I2C_BITRATE_STANDARD>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 vendor-id = <0x8086>; 262 device-id = <0x4b4b>; 263 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 264 interrupt-parent = <&intc>; 265 266 status = "okay"; 267 }; 268 269 i2c5: i2c5 { 270 compatible = "snps,designware-i2c"; 271 clock-frequency = <I2C_BITRATE_STANDARD>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 vendor-id = <0x8086>; 275 device-id = <0x4b4c>; 276 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 277 interrupt-parent = <&intc>; 278 279 status = "okay"; 280 }; 281 282 i2c6: i2c6 { 283 compatible = "snps,designware-i2c"; 284 clock-frequency = <I2C_BITRATE_STANDARD>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 vendor-id = <0x8086>; 288 device-id = <0x4b44>; 289 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 290 interrupt-parent = <&intc>; 291 292 status = "okay"; 293 }; 294 295 i2c7: i2c7 { 296 compatible = "snps,designware-i2c"; 297 clock-frequency = <I2C_BITRATE_STANDARD>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 vendor-id = <0x8086>; 301 device-id = <0x4b45>; 302 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 303 interrupt-parent = <&intc>; 304 305 status = "okay"; 306 }; 307 308 i2c_pse_0: i2c_pse_0 { 309 compatible = "snps,designware-i2c"; 310 clock-frequency = <I2C_BITRATE_STANDARD>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 vendor-id = <0x8086>; 314 device-id = <0x4bb9>; 315 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 316 interrupt-parent = <&intc>; 317 318 status = "okay"; 319 }; 320 321 i2c_pse_1: i2c_pse_1 { 322 compatible = "snps,designware-i2c"; 323 clock-frequency = <I2C_BITRATE_STANDARD>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 vendor-id = <0x8086>; 327 device-id = <0x4bba>; 328 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 329 interrupt-parent = <&intc>; 330 331 status = "okay"; 332 }; 333 334 i2c_pse_2: i2c_pse_2 { 335 compatible = "snps,designware-i2c"; 336 clock-frequency = <I2C_BITRATE_STANDARD>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 vendor-id = <0x8086>; 340 device-id = <0x4bbb>; 341 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 342 interrupt-parent = <&intc>; 343 344 status = "okay"; 345 }; 346 347 i2c_pse_3: i2c_pse_3 { 348 compatible = "snps,designware-i2c"; 349 clock-frequency = <I2C_BITRATE_STANDARD>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 vendor-id = <0x8086>; 353 device-id = <0x4bbc>; 354 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 355 interrupt-parent = <&intc>; 356 357 status = "okay"; 358 }; 359 360 i2c_pse_4: i2c_pse_4 { 361 compatible = "snps,designware-i2c"; 362 clock-frequency = <I2C_BITRATE_STANDARD>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 vendor-id = <0x8086>; 366 device-id = <0x4bbd>; 367 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 368 interrupt-parent = <&intc>; 369 370 status = "okay"; 371 }; 372 373 i2c_pse_5: i2c_pse_5 { 374 compatible = "snps,designware-i2c"; 375 clock-frequency = <I2C_BITRATE_STANDARD>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 vendor-id = <0x8086>; 379 device-id = <0x4bbe>; 380 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 381 interrupt-parent = <&intc>; 382 383 status = "okay"; 384 }; 385 386 i2c_pse_6: i2c_pse_6 { 387 compatible = "snps,designware-i2c"; 388 clock-frequency = <I2C_BITRATE_STANDARD>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 vendor-id = <0x8086>; 392 device-id = <0x4bbf>; 393 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 394 interrupt-parent = <&intc>; 395 396 status = "okay"; 397 }; 398 }; 399 400 soc { 401 #address-cells = <1>; 402 #size-cells = <1>; 403 compatible = "simple-bus"; 404 ranges; 405 406 vtd: vtd@fed91000 { 407 compatible = "intel,vt-d"; 408 409 reg = <0xfed91000 0x1000>; 410 411 status = "okay"; 412 }; 413 414 415 uart1_fixed: uart@fe040000 { 416 compatible = "ns16550"; 417 418 reg = <0xfe040000 0x1000>; 419 reg-shift = <0>; 420 421 clock-frequency = <1843200>; 422 interrupts = <3 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 423 interrupt-parent = <&intc>; 424 425 status = "disabled"; 426 current-speed = <115200>; 427 }; 428 429 uart2_fixed: uart@fe042000 { 430 compatible = "ns16550"; 431 432 reg = <0xfe042000 0x1000>; 433 reg-shift = <0>; 434 435 clock-frequency = <1843200>; 436 interrupts = <4 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 437 interrupt-parent = <&intc>; 438 439 status = "disabled"; 440 current-speed = <115200>; 441 }; 442 443 gpio_0_b: gpio@fd6e0700 { 444 compatible = "intel,gpio"; 445 reg = <0xfd6e0700 0x1000>; 446 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 447 interrupt-parent = <&intc>; 448 449 group-index = <0x0>; 450 gpio-controller; 451 #gpio-cells = <2>; 452 453 ngpios = <24>; 454 pin-offset = <0>; 455 456 status = "okay"; 457 }; 458 459 gpio_0_t: gpio@fd6e08a0 { 460 compatible = "intel,gpio"; 461 reg = <0xfd6e08a0 0x1000>; 462 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 463 interrupt-parent = <&intc>; 464 465 group-index = <0x1>; 466 gpio-controller; 467 #gpio-cells = <2>; 468 469 ngpios = <16>; 470 pin-offset = <26>; 471 472 status = "okay"; 473 }; 474 475 gpio_0_g: gpio@fd6e09a0 { 476 compatible = "intel,gpio"; 477 reg = <0xfd6e09a0 0x1000>; 478 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 479 interrupt-parent = <&intc>; 480 481 group-index = <0x2>; 482 gpio-controller; 483 #gpio-cells = <2>; 484 485 ngpios = <24>; 486 pin-offset = <42>; 487 488 status = "okay"; 489 }; 490 491 gpio_1_v: gpio@fd6d0700 { 492 compatible = "intel,gpio"; 493 reg = <0xfd6d0700 0x1000>; 494 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 495 interrupt-parent = <&intc>; 496 497 group-index = <0x0>; 498 gpio-controller; 499 #gpio-cells = <2>; 500 501 ngpios = <16>; 502 pin-offset = <0>; 503 504 status = "okay"; 505 }; 506 507 gpio_1_h: gpio@fd6d0800 { 508 compatible = "intel,gpio"; 509 reg = <0xfd6d0800 0x1000>; 510 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 511 interrupt-parent = <&intc>; 512 513 group-index = <0x1>; 514 gpio-controller; 515 #gpio-cells = <2>; 516 517 ngpios = <24>; 518 pin-offset = <16>; 519 520 status = "okay"; 521 }; 522 523 gpio_1_d: gpio@fd6d0980 { 524 compatible = "intel,gpio"; 525 reg = <0xfd6d0980 0x1000>; 526 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 527 interrupt-parent = <&intc>; 528 529 group-index = <0x2>; 530 gpio-controller; 531 #gpio-cells = <2>; 532 533 ngpios = <20>; 534 pin-offset = <40>; 535 536 status = "okay"; 537 }; 538 539 gpio_1_u: gpio@fd6d0ad0 { 540 compatible = "intel,gpio"; 541 reg = <0xfd6d0ad0 0x1000>; 542 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 543 interrupt-parent = <&intc>; 544 545 group-index = <0x3>; 546 gpio-controller; 547 #gpio-cells = <2>; 548 549 ngpios = <20>; 550 pin-offset = <61>; 551 552 status = "okay"; 553 }; 554 555 gpio_1_vG: gpio@fd6d0c50 { 556 compatible = "intel,gpio"; 557 reg = <0xfd6d0c50 0x1000>; 558 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 559 interrupt-parent = <&intc>; 560 561 group-index = <0x4>; 562 gpio-controller; 563 #gpio-cells = <2>; 564 565 ngpios = <28>; 566 pin-offset = <85>; 567 568 status = "okay"; 569 }; 570 571 gpio_3_s: gpio@fd6b0810 { 572 compatible = "intel,gpio"; 573 reg = <0xfd6b0810 0x1000>; 574 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 575 interrupt-parent = <&intc>; 576 577 group-index = <0x1>; 578 gpio-controller; 579 #gpio-cells = <2>; 580 581 ngpios = <2>; 582 pin-offset = <17>; 583 584 status = "okay"; 585 }; 586 587 gpio_3_a: gpio@fd6b0830 { 588 compatible = "intel,gpio"; 589 reg = <0xfd6b0830 0x1000>; 590 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 591 interrupt-parent = <&intc>; 592 593 group-index = <0x2>; 594 gpio-controller; 595 #gpio-cells = <2>; 596 597 ngpios = <24>; 598 pin-offset = <25>; 599 600 status = "okay"; 601 }; 602 603 gpio_3_vG: gpio@fd6b09b0 { 604 compatible = "intel,gpio"; 605 reg = <0xfd6b09b0 0x1000>; 606 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 607 interrupt-parent = <&intc>; 608 609 group-index = <0x3>; 610 gpio-controller; 611 #gpio-cells = <2>; 612 613 ngpios = <4>; 614 pin-offset = <49>; 615 616 status = "okay"; 617 }; 618 619 gpio_4_c: gpio@fd6a0700 { 620 compatible = "intel,gpio"; 621 reg = <0xfd6a0700 0x1000>; 622 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 623 interrupt-parent = <&intc>; 624 625 group-index = <0x0>; 626 gpio-controller; 627 #gpio-cells = <2>; 628 629 ngpios = <24>; 630 pin-offset = <0>; 631 632 status = "okay"; 633 }; 634 635 gpio_4_f: gpio@fd6a0880 { 636 compatible = "intel,gpio"; 637 reg = <0xfd6a0880 0x1000>; 638 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 639 interrupt-parent = <&intc>; 640 641 group-index = <0x1>; 642 gpio-controller; 643 #gpio-cells = <2>; 644 645 ngpios = <24>; 646 pin-offset = <24>; 647 648 status = "okay"; 649 }; 650 651 gpio_4_e: gpio@fd6a0a70 { 652 compatible = "intel,gpio"; 653 reg = <0xfd6a0a70 0x1000>; 654 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 655 interrupt-parent = <&intc>; 656 657 group-index = <0x3>; 658 gpio-controller; 659 #gpio-cells = <2>; 660 661 ngpios = <24>; 662 pin-offset = <57>; 663 664 status = "okay"; 665 }; 666 667 gpio_5_r: gpio@fd690700 { 668 compatible = "intel,gpio"; 669 reg = <0xfd690700 0x1000>; 670 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 671 interrupt-parent = <&intc>; 672 673 group-index = <0x0>; 674 gpio-controller; 675 #gpio-cells = <2>; 676 677 ngpios = <8>; 678 pin-offset = <0>; 679 680 status = "okay"; 681 }; 682 683 hpet: hpet@fed00000 { 684 compatible = "intel,hpet"; 685 reg = <0xfed00000 0x400>; 686 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; 687 interrupt-parent = <&intc>; 688 689 status = "okay"; 690 }; 691 692 rtc: counter: rtc@70 { 693 compatible = "motorola,mc146818"; 694 reg = <0x70 0x0D 0x71 0x0D>; 695 interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 696 interrupt-parent = <&intc>; 697 alarms-count = <1>; 698 699 status = "okay"; 700 }; 701 702 }; 703}; 704
