1/* 2 * Copyright (c) 2017-2019 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include "skeleton.dtsi" 8#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h> 9#include <zephyr/dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/pcie/pcie.h> 11 12/ { 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "intel,apollo_lake"; 20 d-cache-line-size = <64>; 21 reg = <0>; 22 }; 23 24 }; 25 26 dram0: memory@0 { 27 device_type = "memory"; 28 reg = <0x0 DT_DRAM_SIZE>; 29 }; 30 31 intc: ioapic@fec00000 { 32 compatible = "intel,ioapic"; 33 reg = <0xfec00000 0x1000>; 34 interrupt-controller; 35 #interrupt-cells = <3>; 36 }; 37 38 pcie0: pcie0 { 39 #address-cells = <1>; 40 #size-cells = <1>; 41 compatible = "intel,pcie"; 42 ranges; 43 44 uart0: uart0 { 45 compatible = "ns16550"; 46 47 vendor-id = <0x8086>; 48 device-id = <0x5abc>; 49 50 reg-shift = <2>; 51 clock-frequency = <1843200>; 52 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 53 interrupt-parent = <&intc>; 54 status = "okay"; 55 current-speed = <115200>; 56 }; 57 58 uart1: uart1 { 59 compatible = "ns16550"; 60 61 vendor-id = <0x8086>; 62 device-id = <0x5abe>; 63 64 reg-shift = <2>; 65 clock-frequency = <1843200>; 66 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 67 interrupt-parent = <&intc>; 68 69 status = "okay"; 70 current-speed = <115200>; 71 }; 72 73 uart2: uart2 { 74 compatible = "ns16550"; 75 76 vendor-id = <0x8086>; 77 device-id = <0x5ac0>; 78 79 reg-shift = <2>; 80 clock-frequency = <1843200>; 81 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 82 interrupt-parent = <&intc>; 83 84 status = "okay"; 85 current-speed = <115200>; 86 }; 87 88 uart3: uart3 { 89 compatible = "ns16550"; 90 91 vendor-id = <0x8086>; 92 device-id = <0x5aee>; 93 94 reg-shift = <2>; 95 clock-frequency = <1843200>; 96 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 97 interrupt-parent = <&intc>; 98 99 status = "okay"; 100 current-speed = <115200>; 101 }; 102 103 i2c0: i2c0 { 104 compatible = "snps,designware-i2c"; 105 clock-frequency = <I2C_BITRATE_STANDARD>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 vendor-id = <0x8086>; 109 device-id = <0x5aac>; 110 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 111 interrupt-parent = <&intc>; 112 113 status = "okay"; 114 }; 115 116 i2c1: i2c1 { 117 compatible = "snps,designware-i2c"; 118 clock-frequency = <I2C_BITRATE_STANDARD>; 119 #address-cells = <1>; 120 #size-cells = <0>; 121 vendor-id = <0x8086>; 122 device-id = <0x5aae>; 123 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 124 interrupt-parent = <&intc>; 125 126 status = "okay"; 127 }; 128 129 i2c2: i2c2 { 130 compatible = "snps,designware-i2c"; 131 clock-frequency = <I2C_BITRATE_STANDARD>; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 vendor-id = <0x8086>; 135 device-id = <0x5ab0>; 136 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 137 interrupt-parent = <&intc>; 138 139 status = "okay"; 140 }; 141 142 i2c3: i2c3 { 143 compatible = "snps,designware-i2c"; 144 clock-frequency = <I2C_BITRATE_STANDARD>; 145 #address-cells = <1>; 146 #size-cells = <0>; 147 vendor-id = <0x8006>; 148 device-id = <0x5ab2>; 149 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 150 interrupt-parent = <&intc>; 151 152 status = "okay"; 153 }; 154 155 i2c4: i2c4 { 156 compatible = "snps,designware-i2c"; 157 clock-frequency = <I2C_BITRATE_STANDARD>; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 vendor-id = <0x8086>; 161 device-id = <0x5ab4>; 162 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 163 interrupt-parent = <&intc>; 164 165 status = "okay"; 166 }; 167 168 i2c5: i2c5{ 169 compatible = "snps,designware-i2c"; 170 clock-frequency = <I2C_BITRATE_STANDARD>; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 vendor-id = <0x8086>; 174 device-id = <0x5ab6>; 175 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 176 interrupt-parent = <&intc>; 177 178 status = "okay"; 179 }; 180 181 i2c6: i2c6 { 182 compatible = "snps,designware-i2c"; 183 clock-frequency = <I2C_BITRATE_STANDARD>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 vendor-id = <0x8086>; 187 device-id = <0x5ab8>; 188 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 189 interrupt-parent = <&intc>; 190 191 status = "okay"; 192 }; 193 194 i2c7: i2c7 { 195 compatible = "snps,designware-i2c"; 196 clock-frequency = <I2C_BITRATE_STANDARD>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 vendor-id = <0x8086>; 200 device-id = <0x5aba>; 201 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 202 interrupt-parent = <&intc>; 203 204 status = "okay"; 205 }; 206 }; 207 208 soc { 209 #address-cells = <1>; 210 #size-cells = <1>; 211 compatible = "simple-bus"; 212 ranges; 213 214 vtd: vtd@fed65000 { 215 compatible = "intel,vt-d"; 216 217 reg = <0xfed65000 0x1000>; 218 219 status = "okay"; 220 }; 221 222 gpio_n_000_031: gpio@d0c50000 { 223 compatible = "intel,gpio"; 224 reg = <0xd0c50000 0x1000>; 225 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 226 interrupt-parent = <&intc>; 227 228 gpio-controller; 229 #gpio-cells = <2>; 230 231 ngpios = <32>; 232 pin-offset = <0>; 233 234 status = "okay"; 235 }; 236 237 gpio_n_032_063: gpio@d0c50001 { 238 compatible = "intel,gpio"; 239 reg = <0xd0c50001 0x1000>; 240 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 241 interrupt-parent = <&intc>; 242 243 gpio-controller; 244 #gpio-cells = <2>; 245 246 ngpios = <32>; 247 pin-offset = <32>; 248 249 status = "okay"; 250 }; 251 252 gpio_n_064_077: gpio@d0c50002 { 253 compatible = "intel,gpio"; 254 reg = <0xd0c50002 0x1000>; 255 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 256 interrupt-parent = <&intc>; 257 258 gpio-controller; 259 #gpio-cells = <2>; 260 261 ngpios = <14>; 262 pin-offset = <64>; 263 264 status = "okay"; 265 }; 266 267 gpio_nw_000_031: gpio@d0c40000 { 268 compatible = "intel,gpio"; 269 reg = <0xd0c40000 0x1000>; 270 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 271 interrupt-parent = <&intc>; 272 273 gpio-controller; 274 #gpio-cells = <2>; 275 276 ngpios = <32>; 277 pin-offset = <0>; 278 279 status = "okay"; 280 }; 281 282 gpio_nw_032_063: gpio@d0c40001 { 283 compatible = "intel,gpio"; 284 reg = <0xd0c40001 0x1000>; 285 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 286 interrupt-parent = <&intc>; 287 288 gpio-controller; 289 #gpio-cells = <2>; 290 291 ngpios = <32>; 292 pin-offset = <32>; 293 294 status = "okay"; 295 }; 296 297 gpio_nw_064_076: gpio@d0c40002 { 298 compatible = "intel,gpio"; 299 reg = <0xd0c40002 0x1000>; 300 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 301 interrupt-parent = <&intc>; 302 303 gpio-controller; 304 #gpio-cells = <2>; 305 306 ngpios = <13>; 307 pin-offset = <64>; 308 309 status = "okay"; 310 }; 311 312 gpio_w_000_031: gpio@d0c70000 { 313 compatible = "intel,gpio"; 314 reg = <0xd0c70000 0x1000>; 315 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 316 interrupt-parent = <&intc>; 317 318 gpio-controller; 319 #gpio-cells = <2>; 320 321 ngpios = <32>; 322 pin-offset = <0>; 323 324 status = "okay"; 325 }; 326 327 gpio_w_032_046: gpio@d0c70001 { 328 compatible = "intel,gpio"; 329 reg = <0xd0c70001 0x1000>; 330 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 331 interrupt-parent = <&intc>; 332 333 gpio-controller; 334 #gpio-cells = <2>; 335 336 ngpios = <15>; 337 pin-offset = <32>; 338 339 status = "okay"; 340 }; 341 342 gpio_sw_000_031: gpio@d0c00000 { 343 compatible = "intel,gpio"; 344 reg = <0xd0c00000 0x1000>; 345 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 346 interrupt-parent = <&intc>; 347 348 gpio-controller; 349 #gpio-cells = <2>; 350 351 ngpios = <32>; 352 pin-offset = <0>; 353 354 status = "okay"; 355 }; 356 357 358 gpio_sw_032_042: gpio@d0c00001 { 359 compatible = "intel,gpio"; 360 reg = <0xd0c00001 0x1000>; 361 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 362 interrupt-parent = <&intc>; 363 364 gpio-controller; 365 #gpio-cells = <2>; 366 367 ngpios = <11>; 368 pin-offset = <32>; 369 370 status = "okay"; 371 }; 372 373 hpet: hpet@fed00000 { 374 compatible = "intel,hpet"; 375 reg = <0xfed00000 0x400>; 376 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; 377 interrupt-parent = <&intc>; 378 379 status = "okay"; 380 }; 381 382 rtc: counter: rtc@70 { 383 compatible = "motorola,mc146818"; 384 reg = <0x70 0x0D 0x71 0x0D>; 385 interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 386 interrupt-parent = <&intc>; 387 alarms-count = <1>; 388 389 status = "okay"; 390 }; 391 }; 392 393 gpio_n: gpio-north { 394 /* n north 78 */ 395 compatible = "intel,apollo-lake-gpio"; 396 #gpio-cells = <2>; 397 gpio-map-mask = <0xffffffff 0xffffffc0>; 398 gpio-map-pass-thru = <0 0x3f>; 399 gpio-map = 400 <0 0 &gpio_n_000_031 0 0>, 401 <1 0 &gpio_n_000_031 1 0>, 402 <2 0 &gpio_n_000_031 2 0>, 403 <3 0 &gpio_n_000_031 3 0>, 404 <4 0 &gpio_n_000_031 4 0>, 405 <5 0 &gpio_n_000_031 5 0>, 406 <6 0 &gpio_n_000_031 6 0>, 407 <7 0 &gpio_n_000_031 7 0>, 408 <8 0 &gpio_n_000_031 8 0>, 409 <9 0 &gpio_n_000_031 9 0>, 410 <10 0 &gpio_n_000_031 10 0>, 411 <11 0 &gpio_n_000_031 11 0>, 412 <12 0 &gpio_n_000_031 12 0>, 413 <13 0 &gpio_n_000_031 13 0>, 414 <14 0 &gpio_n_000_031 14 0>, 415 <15 0 &gpio_n_000_031 15 0>, 416 <16 0 &gpio_n_000_031 16 0>, 417 <17 0 &gpio_n_000_031 17 0>, 418 <18 0 &gpio_n_000_031 18 0>, 419 <19 0 &gpio_n_000_031 19 0>, 420 <20 0 &gpio_n_000_031 20 0>, 421 <21 0 &gpio_n_000_031 21 0>, 422 <22 0 &gpio_n_000_031 22 0>, 423 <23 0 &gpio_n_000_031 23 0>, 424 <24 0 &gpio_n_000_031 24 0>, 425 <25 0 &gpio_n_000_031 25 0>, 426 <26 0 &gpio_n_000_031 26 0>, 427 <27 0 &gpio_n_000_031 27 0>, 428 <28 0 &gpio_n_000_031 28 0>, 429 <29 0 &gpio_n_000_031 29 0>, 430 <30 0 &gpio_n_000_031 30 0>, 431 <31 0 &gpio_n_000_031 31 0>, 432 <32 0 &gpio_n_032_063 0 0>, 433 <33 0 &gpio_n_032_063 1 0>, 434 <34 0 &gpio_n_032_063 2 0>, 435 <35 0 &gpio_n_032_063 3 0>, 436 <36 0 &gpio_n_032_063 4 0>, 437 <37 0 &gpio_n_032_063 5 0>, 438 <38 0 &gpio_n_032_063 6 0>, 439 <39 0 &gpio_n_032_063 7 0>, 440 <40 0 &gpio_n_032_063 8 0>, 441 <41 0 &gpio_n_032_063 9 0>, 442 <42 0 &gpio_n_032_063 10 0>, 443 <43 0 &gpio_n_032_063 11 0>, 444 <44 0 &gpio_n_032_063 12 0>, 445 <45 0 &gpio_n_032_063 13 0>, 446 <46 0 &gpio_n_032_063 14 0>, 447 <47 0 &gpio_n_032_063 15 0>, 448 <48 0 &gpio_n_032_063 16 0>, 449 <49 0 &gpio_n_032_063 17 0>, 450 <50 0 &gpio_n_032_063 18 0>, 451 <51 0 &gpio_n_032_063 19 0>, 452 <52 0 &gpio_n_032_063 20 0>, 453 <53 0 &gpio_n_032_063 21 0>, 454 <54 0 &gpio_n_032_063 22 0>, 455 <55 0 &gpio_n_032_063 23 0>, 456 <56 0 &gpio_n_032_063 24 0>, 457 <57 0 &gpio_n_032_063 25 0>, 458 <58 0 &gpio_n_032_063 26 0>, 459 <59 0 &gpio_n_032_063 27 0>, 460 <60 0 &gpio_n_032_063 28 0>, 461 <61 0 &gpio_n_032_063 29 0>, 462 <62 0 &gpio_n_032_063 30 0>, 463 <63 0 &gpio_n_032_063 31 0>, 464 <64 0 &gpio_n_064_077 0 0>, 465 <65 0 &gpio_n_064_077 1 0>, 466 <66 0 &gpio_n_064_077 2 0>, 467 <67 0 &gpio_n_064_077 3 0>, 468 <68 0 &gpio_n_064_077 4 0>, 469 <69 0 &gpio_n_064_077 5 0>, 470 <70 0 &gpio_n_064_077 6 0>, 471 <71 0 &gpio_n_064_077 7 0>, 472 <72 0 &gpio_n_064_077 8 0>, 473 <73 0 &gpio_n_064_077 9 0>, 474 <74 0 &gpio_n_064_077 10 0>, 475 <75 0 &gpio_n_064_077 11 0>, 476 <76 0 &gpio_n_064_077 12 0>, 477 <77 0 &gpio_n_064_077 13 0>; 478 }; 479 480 gpio_nw: gpio-northwest { 481 /* nw northwest 77 */ 482 compatible = "intel,apollo-lake-gpio"; 483 #gpio-cells = <2>; 484 gpio-map-mask = <0xffffffff 0xffffffc0>; 485 gpio-map-pass-thru = <0 0x3f>; 486 gpio-map = 487 <0 0 &gpio_nw_000_031 0 0>, 488 <1 0 &gpio_nw_000_031 1 0>, 489 <2 0 &gpio_nw_000_031 2 0>, 490 <3 0 &gpio_nw_000_031 3 0>, 491 <4 0 &gpio_nw_000_031 4 0>, 492 <5 0 &gpio_nw_000_031 5 0>, 493 <6 0 &gpio_nw_000_031 6 0>, 494 <7 0 &gpio_nw_000_031 7 0>, 495 <8 0 &gpio_nw_000_031 8 0>, 496 <9 0 &gpio_nw_000_031 9 0>, 497 <10 0 &gpio_nw_000_031 10 0>, 498 <11 0 &gpio_nw_000_031 11 0>, 499 <12 0 &gpio_nw_000_031 12 0>, 500 <13 0 &gpio_nw_000_031 13 0>, 501 <14 0 &gpio_nw_000_031 14 0>, 502 <15 0 &gpio_nw_000_031 15 0>, 503 <16 0 &gpio_nw_000_031 16 0>, 504 <17 0 &gpio_nw_000_031 17 0>, 505 <18 0 &gpio_nw_000_031 18 0>, 506 <19 0 &gpio_nw_000_031 19 0>, 507 <20 0 &gpio_nw_000_031 20 0>, 508 <21 0 &gpio_nw_000_031 21 0>, 509 <22 0 &gpio_nw_000_031 22 0>, 510 <23 0 &gpio_nw_000_031 23 0>, 511 <24 0 &gpio_nw_000_031 24 0>, 512 <25 0 &gpio_nw_000_031 25 0>, 513 <26 0 &gpio_nw_000_031 26 0>, 514 <27 0 &gpio_nw_000_031 27 0>, 515 <28 0 &gpio_nw_000_031 28 0>, 516 <29 0 &gpio_nw_000_031 29 0>, 517 <30 0 &gpio_nw_000_031 30 0>, 518 <31 0 &gpio_nw_000_031 31 0>, 519 <32 0 &gpio_nw_032_063 0 0>, 520 <33 0 &gpio_nw_032_063 1 0>, 521 <34 0 &gpio_nw_032_063 2 0>, 522 <35 0 &gpio_nw_032_063 3 0>, 523 <36 0 &gpio_nw_032_063 4 0>, 524 <37 0 &gpio_nw_032_063 5 0>, 525 <38 0 &gpio_nw_032_063 6 0>, 526 <39 0 &gpio_nw_032_063 7 0>, 527 <40 0 &gpio_nw_032_063 8 0>, 528 <41 0 &gpio_nw_032_063 9 0>, 529 <42 0 &gpio_nw_032_063 10 0>, 530 <43 0 &gpio_nw_032_063 11 0>, 531 <44 0 &gpio_nw_032_063 12 0>, 532 <45 0 &gpio_nw_032_063 13 0>, 533 <46 0 &gpio_nw_032_063 14 0>, 534 <47 0 &gpio_nw_032_063 15 0>, 535 <48 0 &gpio_nw_032_063 16 0>, 536 <49 0 &gpio_nw_032_063 17 0>, 537 <50 0 &gpio_nw_032_063 18 0>, 538 <51 0 &gpio_nw_032_063 19 0>, 539 <52 0 &gpio_nw_032_063 20 0>, 540 <53 0 &gpio_nw_032_063 21 0>, 541 <54 0 &gpio_nw_032_063 22 0>, 542 <55 0 &gpio_nw_032_063 23 0>, 543 <56 0 &gpio_nw_032_063 24 0>, 544 <57 0 &gpio_nw_032_063 25 0>, 545 <58 0 &gpio_nw_032_063 26 0>, 546 <59 0 &gpio_nw_032_063 27 0>, 547 <60 0 &gpio_nw_032_063 28 0>, 548 <61 0 &gpio_nw_032_063 29 0>, 549 <62 0 &gpio_nw_032_063 30 0>, 550 <63 0 &gpio_nw_032_063 31 0>, 551 <64 0 &gpio_nw_064_076 0 0>, 552 <65 0 &gpio_nw_064_076 1 0>, 553 <66 0 &gpio_nw_064_076 2 0>, 554 <67 0 &gpio_nw_064_076 3 0>, 555 <68 0 &gpio_nw_064_076 4 0>, 556 <69 0 &gpio_nw_064_076 5 0>, 557 <70 0 &gpio_nw_064_076 6 0>, 558 <71 0 &gpio_nw_064_076 7 0>, 559 <72 0 &gpio_nw_064_076 8 0>, 560 <73 0 &gpio_nw_064_076 9 0>, 561 <74 0 &gpio_nw_064_076 10 0>, 562 <75 0 &gpio_nw_064_076 11 0>, 563 <76 0 &gpio_nw_064_076 12 0>; 564 }; 565 566 gpio_w: gpio-west { 567 /* w west 47 */ 568 compatible = "intel,apollo-lake-gpio"; 569 #gpio-cells = <2>; 570 gpio-map-mask = <0xffffffff 0xffffffc0>; 571 gpio-map-pass-thru = <0 0x3f>; 572 gpio-map = 573 <0 0 &gpio_w_000_031 0 0>, 574 <1 0 &gpio_w_000_031 1 0>, 575 <2 0 &gpio_w_000_031 2 0>, 576 <3 0 &gpio_w_000_031 3 0>, 577 <4 0 &gpio_w_000_031 4 0>, 578 <5 0 &gpio_w_000_031 5 0>, 579 <6 0 &gpio_w_000_031 6 0>, 580 <7 0 &gpio_w_000_031 7 0>, 581 <8 0 &gpio_w_000_031 8 0>, 582 <9 0 &gpio_w_000_031 9 0>, 583 <10 0 &gpio_w_000_031 10 0>, 584 <11 0 &gpio_w_000_031 11 0>, 585 <12 0 &gpio_w_000_031 12 0>, 586 <13 0 &gpio_w_000_031 13 0>, 587 <14 0 &gpio_w_000_031 14 0>, 588 <15 0 &gpio_w_000_031 15 0>, 589 <16 0 &gpio_w_000_031 16 0>, 590 <17 0 &gpio_w_000_031 17 0>, 591 <18 0 &gpio_w_000_031 18 0>, 592 <19 0 &gpio_w_000_031 19 0>, 593 <20 0 &gpio_w_000_031 20 0>, 594 <21 0 &gpio_w_000_031 21 0>, 595 <22 0 &gpio_w_000_031 22 0>, 596 <23 0 &gpio_w_000_031 23 0>, 597 <24 0 &gpio_w_000_031 24 0>, 598 <25 0 &gpio_w_000_031 25 0>, 599 <26 0 &gpio_w_000_031 26 0>, 600 <27 0 &gpio_w_000_031 27 0>, 601 <28 0 &gpio_w_000_031 28 0>, 602 <29 0 &gpio_w_000_031 29 0>, 603 <30 0 &gpio_w_000_031 30 0>, 604 <31 0 &gpio_w_000_031 31 0>, 605 <32 0 &gpio_w_032_046 0 0>, 606 <33 0 &gpio_w_032_046 1 0>, 607 <34 0 &gpio_w_032_046 2 0>, 608 <35 0 &gpio_w_032_046 3 0>, 609 <36 0 &gpio_w_032_046 4 0>, 610 <37 0 &gpio_w_032_046 5 0>, 611 <38 0 &gpio_w_032_046 6 0>, 612 <39 0 &gpio_w_032_046 7 0>, 613 <40 0 &gpio_w_032_046 8 0>, 614 <41 0 &gpio_w_032_046 9 0>, 615 <42 0 &gpio_w_032_046 10 0>, 616 <43 0 &gpio_w_032_046 11 0>, 617 <44 0 &gpio_w_032_046 12 0>, 618 <45 0 &gpio_w_032_046 13 0>, 619 <46 0 &gpio_w_032_046 14 0>; 620 }; 621 622 gpio_sw: gpio-southwest { 623 /* sw southwest 42 */ 624 compatible = "intel,apollo-lake-gpio"; 625 #gpio-cells = <2>; 626 gpio-map-mask = <0xffffffff 0xffffffc0>; 627 gpio-map-pass-thru = <0 0x3f>; 628 gpio-map = 629 <0 0 &gpio_sw_000_031 0 0>, 630 <1 0 &gpio_sw_000_031 1 0>, 631 <2 0 &gpio_sw_000_031 2 0>, 632 <3 0 &gpio_sw_000_031 3 0>, 633 <4 0 &gpio_sw_000_031 4 0>, 634 <5 0 &gpio_sw_000_031 5 0>, 635 <6 0 &gpio_sw_000_031 6 0>, 636 <7 0 &gpio_sw_000_031 7 0>, 637 <8 0 &gpio_sw_000_031 8 0>, 638 <9 0 &gpio_sw_000_031 9 0>, 639 <10 0 &gpio_sw_000_031 10 0>, 640 <11 0 &gpio_sw_000_031 11 0>, 641 <12 0 &gpio_sw_000_031 12 0>, 642 <13 0 &gpio_sw_000_031 13 0>, 643 <14 0 &gpio_sw_000_031 14 0>, 644 <15 0 &gpio_sw_000_031 15 0>, 645 <16 0 &gpio_sw_000_031 16 0>, 646 <17 0 &gpio_sw_000_031 17 0>, 647 <18 0 &gpio_sw_000_031 18 0>, 648 <19 0 &gpio_sw_000_031 19 0>, 649 <20 0 &gpio_sw_000_031 20 0>, 650 <21 0 &gpio_sw_000_031 21 0>, 651 <22 0 &gpio_sw_000_031 22 0>, 652 <23 0 &gpio_sw_000_031 23 0>, 653 <24 0 &gpio_sw_000_031 24 0>, 654 <25 0 &gpio_sw_000_031 25 0>, 655 <26 0 &gpio_sw_000_031 26 0>, 656 <27 0 &gpio_sw_000_031 27 0>, 657 <28 0 &gpio_sw_000_031 28 0>, 658 <29 0 &gpio_sw_000_031 29 0>, 659 <30 0 &gpio_sw_000_031 30 0>, 660 <31 0 &gpio_sw_000_031 31 0>, 661 <32 0 &gpio_sw_032_042 0 0>, 662 <33 0 &gpio_sw_032_042 1 0>, 663 <34 0 &gpio_sw_032_042 2 0>, 664 <35 0 &gpio_sw_032_042 3 0>, 665 <36 0 &gpio_sw_032_042 4 0>, 666 <37 0 &gpio_sw_032_042 5 0>, 667 <38 0 &gpio_sw_032_042 6 0>, 668 <39 0 &gpio_sw_032_042 7 0>, 669 <40 0 &gpio_sw_032_042 8 0>, 670 <41 0 &gpio_sw_032_042 9 0>, 671 <42 0 &gpio_sw_032_042 10 0>; 672 }; 673}; 674
