1/*
2 * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <skeleton.dtsi>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11
12/ {
13	chosen {
14		zephyr,entropy = &trng;
15	};
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			compatible = "neorv32-cpu";
23			reg = <0>;
24			device_type = "cpu";
25
26			intc: interrupt-controller {
27				compatible = "riscv,cpu-intc";
28				interrupt-controller;
29				#address-cells = <1>;
30				#interrupt-cells = <1>;
31
32				firq: firq {
33					#address-cells = <1>;
34					interrupt-map-mask = <0x0 0xffffffff>;
35					interrupt-map = <
36						0  0 &intc 0 16
37						0  1 &intc 0 17
38						0  2 &intc 0 18
39						0  3 &intc 0 19
40						0  4 &intc 0 20
41						0  5 &intc 0 21
42						0  6 &intc 0 22
43						0  7 &intc 0 23
44						0  8 &intc 0 24
45						0  9 &intc 0 25
46						0 10 &intc 0 26
47						0 11 &intc 0 27
48						0 12 &intc 0 28
49						0 13 &intc 0 29
50						0 14 &intc 0 30
51						0 15 &intc 0 31
52					>;
53					#interrupt-cells = <1>;
54				};
55			};
56		};
57	};
58
59	soc {
60		compatible = "simple-bus";
61		interrupt-parent = <&firq>;
62		#address-cells = <1>;
63		#size-cells = <1>;
64		ranges;
65
66		mtimer: timer@ffffff90 {
67			compatible = "neorv32-machine-timer";
68			reg = <0xffffff90 0x10>;
69			interrupts = <7>;
70		};
71
72		uart0: serial@ffffffa0 {
73			compatible = "neorv32-uart";
74			status = "disabled";
75			reg = <0xffffffa0 8>;
76			interrupts = <2>, <3>;
77			interrupt-names = "RX", "TX";
78			syscon = <&sysinfo>;
79		};
80
81		trng: rng@ffffffb8 {
82			compatible = "neorv32-trng";
83			status = "disabled";
84			reg = <0xffffffb8 4>;
85			syscon = <&sysinfo>;
86		};
87
88		gpio: gpio {
89			compatible = "simple-bus";
90			gpio-map-mask = <0xffffffe0 0xffffffc0>;
91			gpio-map-pass-thru = <0x1f 0x3f>;
92			gpio-map = <
93				0x00 0x0 &gpio_lo 0x0 0x0
94				0x20 0x0 &gpio_hi 0x0 0x0
95			>;
96			#gpio-cells = <2>;
97			#address-cells = <1>;
98			#size-cells = <1>;
99			ranges;
100
101			gpio_lo: gpio@ffffffc0 {
102				compatible = "neorv32-gpio";
103				status = "disabled";
104				reg = <0xffffffc0 4 0xffffffc8 4>;
105				reg-names = "input", "output";
106				gpio-controller;
107				ngpios = <32>;
108				syscon = <&sysinfo>;
109				#gpio-cells = <2>;
110			};
111
112			gpio_hi: gpio@ffffffc4 {
113				compatible = "neorv32-gpio";
114				status = "disabled";
115				reg = <0xffffffc4 4 0xffffffcc 4>;
116				reg-names = "input", "output";
117				gpio-controller;
118				ngpios = <32>;
119				syscon = <&sysinfo>;
120				#gpio-cells = <2>;
121			};
122		};
123
124		uart1: serial@ffffffd0 {
125			compatible = "neorv32-uart";
126			status = "disabled";
127			reg = <0xffffffd0 8>;
128			interrupts = <4>, <5>;
129			interrupt-names = "RX", "TX";
130			syscon = <&sysinfo>;
131		};
132
133		sysinfo: syscon@ffffffe0 {
134			compatible = "neorv-sysinfo", "syscon";
135			status = "okay";
136			reg = <0xffffffe0 32>;
137		};
138	};
139};
140