1# Copyright (c) 2018, Google LLC.
2# Copyright (c) 2021, Microchip Technology Inc.
3# SPDX-License-Identifier: Apache-2.0
4
5description: Microchip XEC QMSPI controller with local DMA
6
7compatible: "microchip,xec-qmspi-ldma"
8
9include: [spi-controller.yaml, pinctrl-device.yaml]
10
11properties:
12  reg:
13    required: true
14
15  clocks:
16    required: true
17
18  interrupts:
19    required: true
20
21  girqs:
22    type: array
23    required: true
24    description: |
25      An array of integers encoding each interrupt signal connection.
26      This information includes the aggregated GIRQ number, GIRQ bit
27      position, aggregated GIRQ NVIC connection, and direct NVIC
28      connection of the GIRQ bit.
29
30  pinctrl-0:
31    required: true
32
33  pinctrl-names:
34    required: true
35
36  lines:
37    type: int
38    description: |
39      QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40      MOSI and MISO or half-duplex on MOSI only. Lines set to 2
41      or 4 indicate dual or quad I/O modes.
42      Defaults to 1 for full duplex driver's support for full-duplex spi.
43    enum:
44      - 1
45      - 2
46      - 4
47
48  chip-select:
49    type: int
50    description: |
51      Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
52      Ports 1 and 2 implement CS0# only. Defaults to CS0#.
53
54  dcsckon:
55    type: int
56    description: |
57      Delay in QMSPI main clocks from CS# assertion to first clock edge.
58      If not present use hardware default value. Refer to chip documention
59      for QMSPI input clock frequency.
60
61  dckcsoff:
62    type: int
63    description: |
64      Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
65      If not present use hardware default value. Refer to chip documention
66      for QMSPI input clock frequency.
67
68  dldh:
69    type: int
70    description: |
71      Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
72      and WP#. If not present use hardware default value. Refer to chip
73      documentation for QMSPI input clock frequency.
74
75  dcsda:
76    type: int
77    description: |
78      Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
79      If not present use hardware default value. Refer to chip documention
80      for QMSPI input clock frequency.
81
82  cs1-freq:
83    type: int
84    description: |
85      Allows different frequencies for CS#0 and CS1# devices. This applies
86      to ports implementing CS1#.
87
88  tctradj:
89    type: int
90    description: |
91      An optional signed 8-bit value for adjusting the QMSPI control signal
92      timing tap.
93
94  tsckadj:
95    type: int
96    description: |
97      An optional signed 8-bit value for adjusting the QMSPI clock signal
98      timing tap.
99