1# Copyright (c) 2023 Enphase Energy
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  TI K3 pinctrl node.
6
7  Pins can be configured using the following macro "K3_PINMUX(offset, value, mux_mode)".
8  offset - the pin attribute register offset from the base address.
9  value - one of the following:
10    PIN_OUTPUT
11    PIN_OUTPUT_PULLUP
12    PIN_OUTPUT_PULLDOWN
13    PIN_INPUT
14    PIN_INPUT_PULLUP
15    PIN_INPUT_PULLDOWN
16  mux_mode - The mux mode for the pin, MUX_MODE_0 -> MUX_MODE_9.
17  e.g. for AM62x the pinctrl base address is 0xf4000.
18       The default UART0_RX pin is located at 0x000f41c8 (mux mode 0).
19       So the configuration would be "K3_PINMUX(0x1c8, PIN_INPUT, MUX_MODE_0)".
20
21compatible: "ti,k3-pinctrl"
22
23include: base.yaml
24
25properties:
26  reg:
27    required: true
28
29child-binding:
30  description: |
31    This binding gives a base representation of the TI K3
32    pin configuration.
33
34  properties:
35    pinmux:
36      required: true
37      type: array
38      description: |
39        TI K3 pin configuration.
40