1# Copyright (c) 2022 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
6  nodes can be autogenerated using the MCUXpresso config tools combined with
7  the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
8  fields in a group select the pins to be configured, and the remaining
9  devicetree properties set configuration values for those pins
10  for example, here is an group configuring LPUART1 pins:
11
12  group0 {
13    pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx,
14      &iomuxc_gpio_ad_b0_13_lpuart1_rx>;
15    drive-strength = "r0-6";
16    slew-rate = "slow";
17    nxp,speed = "100-mhz";
18  };
19
20  This will select GPIO_AD_B0_12 as LPUART1 TX, and GPIO_AD_B0_13 as LPUART1 RX.
21  Both pins will be configured with a weak latch, drive strength of "r0-6",
22  slow slew rate, and 100 MHZ speed.
23  Note that the soc level iomuxc dts file can be examined to find the possible
24  pinmux options. Here are the affects of each property on the
25  IOMUXC SW_PAD_CTL register:
26  input-schmitt-enable: HYS=1
27  drive-open-drain: ODE=1
28  input-enable: SION=1 (in SW_MUX_CTL_PAD register)
29  bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
30  bias-pull-up: PUE=1, PUS=<bias-pull-up-value>
31  bias-disable: PKE=0
32  slew-rate: SRE=<enum_idx>
33  drive-strength: DSE=<enum_idx>
34  nxp,speed: SPEED=<enum_idx>
35
36  If only required properties are supplied, the pin will have the following
37  configuration:
38  HYS=0,
39  ODE=0,
40  SION=0,
41  PUE=0,
42  PUS=0,
43  PKE=1,
44  SRE=<slew-rate>,
45  DSE=<drive-strength>,
46  SPEED=<nxp,speed>
47
48
49compatible: "nxp,mcux-rt-pinctrl"
50
51include: base.yaml
52
53child-binding:
54  description: MCUX RT pin controller pin group
55  child-binding:
56    description: |
57      MCUX RT pin controller pin configuration node.
58
59    include:
60      - name: pincfg-node.yaml
61        property-allowlist:
62          - input-schmitt-enable
63          - drive-open-drain
64          - input-enable
65          - bias-disable
66          - bias-pull-down
67          - bias-pull-up
68
69    properties:
70      pinmux:
71        required: true
72        type: phandles
73        description: |
74          Pin mux selections for this group. See the soc level iomuxc DTSI file
75          for a defined list of these options.
76      drive-strength:
77        required: true
78        type: string
79        enum:
80          - "disabled"
81          - "r0"
82          - "r0-2"
83          - "r0-3"
84          - "r0-4"
85          - "r0-5"
86          - "r0-6"
87          - "r0-7"
88        description: |
89          Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
90          the drive strength is expressed as a output impedance at a given voltage,
91          but maximum current values can be calculated from these impedances
92          for a specific load impedance.
93          000 DSE_0_output_driver_disabled_ — output driver disabled
94          001 DSE_1_R0_1 — 157 Ohm impedance @3.3V, 260 Ohm impedance @1.8V
95          010 DSE_2_R0_2 — 78 Ohm @3.3V, 130 Ohm @1.8V
96          011 DSE_3_R0_3 — 53 Ohm @3.3V, 88 Ohm @1.8V
97          100 DSE_4_R0_4 — 39 Ohm @3.3V, 65 Ohm @1.8V
98          101 DSE_5_R0_5 — 32 Ohm @3.3V, 52 Ohm @1.8V
99          110 DSE_6_R0_6 — 32 Ohm @3.3V, 43 Ohm @1.8V
100          111 DSE_7_R0_7 — 26 Ohm @3.3V, 37 Ohm @1.8V
101      bias-pull-up-value:
102        type: string
103        default: "47k"
104        enum:
105          - "unused"
106          - "47k"
107          - "100k"
108          - "22k"
109        description: |
110          Select the value of the pull up resistor present on this pin
111          Corresponds to the PUS field in the IOMUXC peripheral.
112          47k resistor selected as default due to this being the default pullup
113          value on most SOC pins
114          00 Unused- no change will be applied to pin
115          01 PUS_1_47K_Ohm_Pull_Up — 47K Ohm Pull Up
116          10 PUS_2_100K_Ohm_Pull_Up — 100K Ohm Pull Up
117          11 PUS_2_22K_Ohm_Pull_Up — 22K Ohm Pull Up
118
119      bias-pull-down-value:
120        type: string
121        default: "100k"
122        enum:
123          - "100k"
124        description: |
125          Select the value of the pull up resistor present on this pin
126          Corresponds to the PUS field in the IOMUXC peripheral. 100k is
127          currently the only supported pull down resistance.
128          00 PUS_0_100K_Ohm_Pull_Down - 100K Ohm Pull Down
129      slew-rate:
130        required: true
131        type: string
132        enum:
133          - "slow"
134          - "fast"
135        description: |
136          Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
137          0 SRE_0_Slow_Slew_Rate — Slow Slew Rate
138          1 SRE_1_Fast_Slew_Rate — Fast Slew Rate
139      nxp,speed:
140        type: string
141        enum:
142          - "50-mhz"
143          - "100-mhz"
144          - "150-mhz"
145          - "200-mhz"
146        description: |
147          Sets pin speed. Corresponds to SPEED field in IOMUXC peripheral
148          00 SPEED_0_low_50MHz_ — low(50MHz)
149          01 SPEED_1_medium_100MHz_ — medium(100MHz)
150          10 SPEED_2_medium_150MHz_ — medium(150MHz)
151          11 SPEED_3_max_200MHz_ — max(200MHz)
152