1# Copyright (c) 2022 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  The node has the 'pinctrl' node label set in MCUX SoC's devicetree. These
6  nodes can be autogenerated using the MCUXpresso config tools combined with
7  the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
8  fields in a group select the pins to be configured, and the remaining
9  devicetree properties set configuration values for those pins
10  for example, here is an group configuring LPUART1 pins:
11
12  group0 {
13    pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx,
14      &iomuxc_uart2_txd_uart_tx_uart2_tx>;
15      bias-pull-up;
16      slew-rate = "slow";
17      drive-strength = "x1";
18  };
19
20  This will select UART2_RXD as UART2 rx, and UART2_TXD as UART2 tx.
21  Both pins will be configured with a slow slew rate, and x1 drive
22  strength.
23  Note that the soc level iomuxc dts file can be examined to find the possible
24  pinmux options. Here are the affects of each property on the
25  IOMUXC SW_PAD_CTL register:
26  input-schmitt-enable: HYS=1
27  drive-open-drain: OD=1
28  bias-pull-down: PD=0
29  bias-pull-up: PU
30  slew-rate: FSEL1=<enum_idx>
31  drive-strength: DSE=<enum_idx>
32  input-enable: SION=1 (in SW_MUX_CTL_PAD register)
33
34  If only required properties are supplied, the pin will have the following
35  configuration:
36  HYS=0,
37  PD=0
38  PU=0
39  OD=0,
40  FSEL1=<slew-rate>,
41  DSE=<drive-strength>,
42  SION=0,
43
44
45compatible: "nxp,imx93-pinctrl"
46
47include: base.yaml
48
49child-binding:
50  description: iMX pin controller pin group
51  child-binding:
52    description: |
53      iMX pin controller pin configuration node.
54
55    include:
56      - name: pincfg-node.yaml
57        property-allowlist:
58          - input-schmitt-enable
59          - drive-open-drain
60          - input-enable
61          - bias-pull-up
62          - bias-pull-down
63
64    properties:
65      pinmux:
66        required: true
67        type: phandles
68        description: |
69          Pin mux selections for this group. See the soc level iomuxc DTSI file
70          for a defined list of these options.
71      drive-strength:
72        required: true
73        type: string
74        enum:
75          - "x0"
76          - "x1"
77          - "x2"
78          - "x3"
79          - "x4"
80          - "x5"
81          - "x6"
82        description: |
83          Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
84          00_0000 X0, No driver
85          00_0001 X1
86          00_0011 X2
87          00_0111 X3
88          00_1111 X4
89          01_1111 X5
90          11_1111 X6
91      slew-rate:
92        required: true
93        type: string
94        enum:
95          - "slow"
96          - "slightly_slow"
97          - "slightly_fast"
98          - "fast"
99        description: |
100          Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
101          0 SLOW — Slow Frequency Slew Rate
102          1 Slightly SLOW — Slightly Slow Frequency Slew Rate
103          2 Slightly FAST — Slightly Fast Frequency Slew Rate
104          3 FAST — Fast Frequency Slew Rate
105