1# Copyright (c) 2020 Linaro Limited
2# Copyright (c) 2021 Microchip Technology Inc.
3# SPDX-License-Identifier: Apache-2.0
4
5description: |
6    Microchip XEC Pin controller Node
7    Based on pincfg-node.yaml binding.
8    The MCHP XEC pin controller is a singleton node responsible for controlling
9    pin function selection and pin properties. For example, you can use this
10    node to select peripheral pin functions.
11
12    The node has the 'pinctrl' node label set in your SoC's devicetree,
13    so you can modify it like this:
14
15      &pinctrl {
16              /* your modifications go here */
17      };
18
19    All device pin configurations should be placed in child nodes of the
20    'pinctrl' node, as in the spi0 example shown at the end:
21
22    A group can also specify shared pin properties common to all the specified
23    pins, such as the 'bias-pull-up' property in group 2. Here is a list of
24    supported standard pin properties:
25
26    - bias-disable: Disable pull-up/down (default behavior, not required).
27    - bias-pull-down: Enable pull-down resistor.
28    - bias-pull-up: Enable pull-up resistor.
29    - drive-push-pull: Output driver is push-pull (default, not required).
30    - drive-open-drain: Output driver is open-drain.
31    - output-high: Set output state high when pin configured.
32    - output-low: Set output state low when pin configured.
33
34    Custom pin properties for drive strength and slew rate are available:
35    - drive-strength
36    - slew-rate
37
38    Driver strength and slew rate hardware defaults vary by SoC and pin.
39
40    An example for MEC172x family, include the chip level pinctrl
41    DTSI file in the board level DTS:
42
43      #include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>
44
45    We want to use the shared SPI port of the MEC172x QMSPI controller
46    and want the chip select 0 to be open-drain.
47
48    To change a pin's pinctrl default properties add a reference to the
49    pin in the board's DTS file and set the properties.
50
51      &spi0 {
52        pinctrl-0 = < &shd_cs0_n_gpio055
53                      &shd_clk_gpio056
54                      &shd_io0_gpio223
55                      &shd_io1_gpio224
56                      &shd_io3_gpio016 >;
57        pinctrl-names = "default";
58      }
59
60      &shd_cs0_n_gpio055 {
61        drive-open-drain;
62      };
63
64compatible: "microchip,xec-pinctrl"
65
66include: base.yaml
67
68properties:
69  reg:
70    required: true
71
72child-binding:
73  description: |
74    This binding gives a base representation of the Microchip XEC pins
75    configuration
76
77  include:
78    - name: pincfg-node.yaml
79      property-allowlist:
80        - bias-disable
81        - bias-pull-down
82        - bias-pull-up
83        - drive-push-pull
84        - drive-open-drain
85        - low-power-enable
86        - output-disable
87        - output-enable
88        - output-high
89        - output-low
90
91  properties:
92    pinmux:
93      type: int
94      required: true
95      description: Pinmux selection
96
97    slew-rate:
98      type: string
99      default: "no-change"
100      enum:
101        - "no-change"
102        - "low-speed"
103        - "high-speed"
104      description: |
105        Pin speed. The default value of slew-rate is the SoC power-on-reset
106        value. Please refer to the data sheet as a small number of pins
107        may have a different default and some pins do not implement
108        slew rate adjustment.
109
110    drive-strength:
111      type: string
112      default: "no-change"
113      enum:
114        - "no-change"
115        - "1x"
116        - "2x"
117        - "4x"
118        - "6x"
119      description: |
120        Pin output drive strength for PIO and PIO-24 pin types. Default
121        is "1x" for most pins. PIO pins are 2, 4, 8, or 12 mA. PIO-24 pins
122        are 4, 8, 16, or 24 mA. Please refer to the data sheet for each
123        pin's PIO type and default drive strength.
124
125    microchip,output-func-invert:
126      type: boolean
127      description:
128        Invert polarity of an output alternate function. Input functions
129        are not affected.
130