1# Copyright (c) 2020, Linaro limited 2# SPDX-License-Identifier: Apache-2.0 3 4description: | 5 STM32 QSPI Flash controller supporting the JEDEC CFI interface 6 7 Representation of a serial flash on a quadspi bus: 8 9 mx25r6435f: qspi-nor-flash@0 { 10 compatible = "st,stm32-qspi-nor"; 11 reg = <0>; 12 qspi-max-frequency = <80000000>; 13 size = <0x4000000>; 14 reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>; 15 reset-gpios-duration = <1>; 16 spi-bus-width = <4>; 17 status = "okay"; 18 }; 19 20compatible: "st,stm32-qspi-nor" 21 22include: ["flash-controller.yaml", "jedec,jesd216.yaml"] 23 24on-bus: qspi 25 26properties: 27 reg: 28 required: true 29 qspi-max-frequency: 30 type: int 31 required: true 32 description: Maximum clock frequency of device's QSPI interface in Hz 33 size: 34 required: true 35 description: Flash Memory size in bits 36 reset-gpios: 37 type: phandle-array 38 description: RESETn pin 39 reset-gpios-duration: 40 type: int 41 description: The duration (in ms) for the flash memory reset pulse 42 reset-cmd: 43 type: boolean 44 description: Send reset command on initialization 45 reset-cmd-wait: 46 type: int 47 default: 10 48 description: The duration (in us) to wait after reset command 49 spi-bus-width: 50 type: int 51 description: The width of (Q)SPI bus to which flash memory is connected. 52 Now only value of 4 (when using SIO[0123]) is supported. 53 writeoc: 54 type: string 55 enum: 56 - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32) 57 - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38) 58 description: | 59 The value encodes number of I/O lines used for the opcode, 60 address, and data. 61 62 There is no info about quad page program opcodes in the SFDP 63 tables, hence it has been assumed that NOR flash memory 64 supporting 1-4-4 mode also would support fast page programming. 65 66 If absent, then 1-4-4 program page is used in quad mode. 67