1# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 DMA controller (V2)
6
7  It is present on stm32 devices like stm32L4 or stm32WB.
8  This DMA controller includes several channels with different requests.
9  DMA clients connected to the STM32 DMA controller must use the format
10  described in the dma.txt file, using a four-cell specifier for each
11  capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
12  DMA clients connected to the STM32 DMA controller must use the format
13  described in the dma.txt file, using a 3-cell specifier for each
14  channel: a phandle to the DMA controller plus the following four integer cells:
15    1. channel: the dma stream from 1 to <dma-requests>
16    2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
17    this value is 0 for Memory-to-memory transfers
18    or a value between <1> .. <dma-generators> (not supported yet)
19    or a value beweeen <dma-generators>+1  ..  <dma-generators>+<dma-requests>
20    3. channel-config: A 32bit mask specifying the DMA channel configuration
21    A name custom DMA flags for channel configuration is used
22    which is device dependent see stm32_dma.h:
23      -bit 5 : DMA  cyclic mode config
24                0x0: STM32_DMA_MODE_NORMAL
25                0x1: STM32_DMA_MODE_CYCLIC
26      -bit 6-7 : Direction (see dma.h)
27                0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
28                0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
29                0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
30                0x3: reserved for PERIPH to PERIPH
31      -bit 9 : Peripheral Increment Address
32               0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
33               0x1: STM32_DMA_PERIPH_INC: increment address between transfers
34      -bit 10 : Memory Increment Address
35               0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
36               0x1: STM32_DMA_MEM_INC: increment address between transfers
37      -bit 11-12 : Peripheral data size
38               0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
39               0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
40               0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
41               0x3: reserved
42      -bit 13-14 : Memory data size
43               0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
44               0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
45               0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
46               0x3: reserved
47      -bit 15: Reserved
48      -bit 16-17 : Priority level
49               0x0: STM32_DMA_PRIORITY_LOW: low
50               0x1: STM32_DMA_PRIORITY_MEDIUM: medium
51               0x2: STM32_DMA_PRIORITY_HIGH: high
52               0x3: STM32_DMA_PRIORITY_VERY_HIGH: very high
53
54  Example of dma usual combination for peripheral transfer
55       #define STM32_DMA_PERIPH_TX	(STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC)
56       #define STM32_DMA_PERIPH_RX	(STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC)
57
58  Example of dma node for stm32wb55x
59     dma2: dma-controller@40020400 {
60         compatible = "st,stm32-dma-v2";
61         ...
62         dma-requests = <7>;
63         status = "disabled";
64        };
65
66  For the client part, example for stm32l476 on DMA1 instance
67    Tx using channel 3 with request 1
68    Rx using channel 2 with request 1
69    spi1 {
70     compatible = "st,stm32-spi";
71     dmas = <&dma1 3 1 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
72            <&dma1 2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
73     dma-names = "tx", "rx";
74    };
75
76compatible: "st,stm32-dma-v2"
77
78include: st,stm32-dma.yaml
79
80properties:
81  "#dma-cells":
82    const: 3
83
84# Parameter syntax of stm32 follows the dma client dts syntax
85# in the Linux kernel declared in
86# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
87
88dma-cells:
89  - channel
90  - slot
91  - channel-config
92