1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 Reset and Clock controller node.
6  This node is in charge of system clock ('SYSCLK') source selection and controlling
7  clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
8
9  Configuring STM32 Reset and Clock controller node:
10
11  System clock source should be selected amongst the clock nodes available in "clocks"
12  node (typically 'clk_hse, clk_hsi', 'pll', ...).
13  Core clock frequency should also be defined, using "clock-frequency" property.
14  Note:
15          Core clock frequency  = SYSCLK / AHB prescaler
16  Last, peripheral bus clocks (typically PCLK1, PCLK2) should be configured using matching
17  prescaler properties.
18  Here is an example of correctly configured rcc node:
19  &rcc {
20           clocks = <&pll>;  /* Select 80MHz pll as SYSCLK source */
21           ahb-prescaler = <2>;
22           clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23           apb1-presacler = <1>;
24           apb2-presacler = <1>;
25  }
26
27  Specifying a gated clock:
28
29  To specify a gated clock, a peripheral should define a "clocks" property encoded
30  in the following way:
31  ... {
32           ...
33           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
34           ...
35  }
36  After the phandle referring to rcc node, the first index specifies the registers of
37  the bus controlling the peripheral and the second index specifies the bit used to
38  control the peripheral clock in that bus register.
39  The gated clock is required when accessing to the peripheral controller is needed
40  (generally for configuring the device). If dual clock domain is not used, it is
41  also used for peripheral operation.
42
43  Specifying a domain clock source:
44
45  Specifying a domain source clock could be done by adding a clock specifier to the
46  clock property:
47  ... {
48           ...
49           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
50                        <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
51           ...
52  }
53  In this example, I2C1 device is assigned HSI as domain clock source.
54  Domain clock is independent from the bus/gatted clock and allows access to the device's
55  register while the gated clock is off. As it doesn't feed the peripheral's controller, it
56  allows peripheral operation, but can't be used for peripheral configuration.
57  It is peripheral driver's responsibility to querry and use clock source information in
58  accordance with clock_control API specifications.
59
60  Since the peripheral subsystem rate is dictated by the clock used for peripheral
61  operation, same clock should be used in calls to `clock_control_get_rate()`
62
63  Note 1: No additional specifier means gating clock is also the clock source (ie
64          'PCLK/PCLK1/PCLK2' depending on the device). There is no need to add a second
65          cell to explicitly set it.
66  Note 2: Default peripheral clock configuration (ie the one provided in *.dsti files)
67          should be the one matching SoC reset state. Confere reference manual to check
68          what is the reset value of the clock source for each peripheral.
69
70compatible: "st,stm32-rcc"
71
72include: [clock-controller.yaml, base.yaml]
73
74properties:
75  reg:
76    required: true
77
78  "#clock-cells":
79    const: 2
80
81  clock-frequency:
82    required: true
83    type: int
84    description: |
85      default frequency in Hz for clock output
86
87  ahb-prescaler:
88    type: int
89    required: true
90    enum:
91      - 1
92      - 2
93      - 4
94      - 8
95      - 16
96      - 64
97      - 128
98      - 256
99      - 512
100    description: |
101        AHB prescaler. Defines actual core clock frequency (HCLK)
102        based on system frequency input.
103        The HCLK clocks CPU, AHB, memories and DMA.
104
105  apb1-prescaler:
106    type: int
107    required: true
108    enum:
109      - 1
110      - 2
111      - 4
112      - 8
113      - 16
114
115  apb2-prescaler:
116    type: int
117    required: true
118    enum:
119      - 1
120      - 2
121      - 4
122      - 8
123      - 16
124
125  undershoot-prevention:
126    type: boolean
127    description: |
128      On some parts, it could be required to set up highest core frequencies
129      (>80MHz) in two steps in order to prevent undershoot.
130      This is done by applying an intermediate AHB prescaler before switching
131      System Clock source to PLL. Once done, prescaler is set back to expected
132      value.
133
134clock-cells:
135  - bus
136  - bits
137