1/*
2 * Copyright 2021 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm64/armv8-a.dtsi>
8#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9#include <mem.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18		cpu@0 {
19			device_type = "cpu";
20			compatible = "arm,cortex-a72";
21			reg = <0>;
22		};
23		cpu@1 {
24			device_type = "cpu";
25			compatible = "arm,cortex-a72";
26			reg = <1>;
27		};
28		cpu@2 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a72";
31			reg = <2>;
32		};
33		cpu@3 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a72";
36			reg = <3>;
37		};
38	};
39
40	gic: interrupt-controller@1410000 {
41		compatible = "arm,gic";
42		reg = <0x01410000 0x10000>, /* GICD */
43		      <0x0142f000 0x1000>; /* GICC */
44		interrupt-controller;
45		#interrupt-cells = <4>;
46		status = "okay";
47	};
48
49	psci: psci {
50		compatible = "arm,psci-0.2";
51		method = "smc";
52	};
53
54	sram0: memory@c0000000 {
55		       reg = <0xc0000000 DT_SIZE_M(1)>;
56	       };
57
58	timer {
59		compatible = "arm,armv8-timer";
60		interrupt-parent = <&gic>;
61		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
62			      IRQ_DEFAULT_PRIORITY>,
63			     <GIC_PPI 14 IRQ_TYPE_LEVEL
64			      IRQ_DEFAULT_PRIORITY>,
65			     <GIC_PPI 11 IRQ_TYPE_LEVEL
66			      IRQ_DEFAULT_PRIORITY>,
67			     <GIC_PPI 10 IRQ_TYPE_LEVEL
68			      IRQ_DEFAULT_PRIORITY>;
69	};
70
71	uart1: serial@21c0600 {
72			compatible = "fsl,ns16550", "ns16550";
73			reg = <0x21c0600 0x100>;
74			interrupt-parent = <&gic>;
75			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
76			clock-frequency = <350000000>;
77			reg-shift = <2>;
78			status = "disabled";
79		};
80};
81