1/*
2 * Copyright (c) 2020 Teslabs Engineering S.L.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/h7/stm32h7.dtsi>
8#include <zephyr/dt-bindings/display/panel.h>
9
10/ {
11	soc {
12		compatible = "st,stm32h743", "st,stm32h7", "simple-bus";
13
14		flash-controller@52002000 {
15			flash0: flash@8000000 {
16				compatible = "st,stm32-nv-flash", "soc-nv-flash";
17				write-block-size = <32>;
18				erase-block-size = <DT_SIZE_K(128)>;
19				/* maximum erase time for a 128K sector */
20				max-erase-time = <4000>;
21			};
22		};
23
24		adc3: adc@58026000 {
25			vbat-channel = <17>;
26			temp-channel = <18>;
27			vref-channel = <19>;
28		};
29
30		dmamux1: dmamux@40020800 {
31			dma-requests= <107>;
32		};
33
34		dmamux2: dmamux@58025800 {
35			dma-requests= <107>;
36		};
37
38		usbotg_fs: usb@40080000 {
39			compatible = "st,stm32-otgfs";
40			reg = <0x40080000 0x40000>;
41			interrupts = <101 0>, <98 0>, <99 0>;
42			interrupt-names = "otgfs", "ep1_out", "ep1_in";
43			num-bidir-endpoints = <9>;
44			ram-size = <4096>;
45			maximum-speed = "full-speed";
46			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
47				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
48			phys = <&otghs_fs_phy>;
49			status = "disabled";
50		};
51
52		ltdc: display-controller@50001000 {
53			compatible = "st,stm32-ltdc";
54			reg = <0x50001000 0x200>;
55			interrupts = <88 0>, <89 0>;
56			interrupt-names = "ltdc", "ltdc_er";
57			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
58			status = "disabled";
59		};
60
61		rtc@58004000 {
62			bbram: backup_regs {
63				compatible = "st,stm32-bbram";
64				st,backup-regs = <32>;
65				status = "disabled";
66			};
67		};
68	};
69
70	/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
71	sram0: memory@24000000 {
72		reg = <0x24000000 DT_SIZE_K(512)>;
73		compatible = "mmio-sram";
74	};
75
76	/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
77	sram1: memory@30000000 {
78		reg = <0x30000000 DT_SIZE_K(128)>;
79		compatible = "zephyr,memory-region", "mmio-sram";
80		zephyr,memory-region = "SRAM1";
81	};
82
83	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
84	sram2: memory@30020000 {
85		compatible = "zephyr,memory-region", "mmio-sram";
86		reg = <0x30020000 DT_SIZE_K(128)>;
87		zephyr,memory-region = "SRAM2";
88	};
89
90	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
91	sram3: memory@30040000 {
92		compatible = "zephyr,memory-region", "mmio-sram";
93		reg = <0x30040000 DT_SIZE_K(32)>;
94		zephyr,memory-region = "SRAM3";
95	};
96
97	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
98	sram4: memory@38000000 {
99		reg = <0x38000000 DT_SIZE_K(64)>;
100		compatible = "zephyr,memory-region", "mmio-sram";
101		zephyr,memory-region = "SRAM4";
102	};
103
104	dtcm: memory@20000000 {
105		compatible = "zephyr,memory-region", "arm,dtcm";
106		reg = <0x20000000 DT_SIZE_K(128)>;
107		zephyr,memory-region = "DTCM";
108	};
109
110	otghs_fs_phy: otghs_fs_phy {
111		compatible = "usb-nop-xceiv";
112		#phy-cells = <0>;
113	};
114
115	vref: vref {
116		io-channels = <&adc3 19>;
117	};
118
119	vbat: vbat {
120		io-channels = <&adc3 17>;
121	};
122};
123