1/*
2 * Copyright (c) 2020, Seagate Technology LLC
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#include <arm/armv6-m.dtsi>
7#include <zephyr/dt-bindings/clock/lpc11u6x_clock.h>
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <mem.h>
10
11/ {
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu0: cpu@0 {
17			compatible = "arm,cortex-m0+";
18			reg = <0>;
19		};
20	};
21
22	sram0:memory@10000000 {
23		compatible = "mmio-sram";
24	};
25
26	sram1:memory@20000000 {
27		compatible = "zephyr,memory-region", "mmio-sram";
28		reg = <0x20000000 0x800>;
29		zephyr,memory-region = "SRAM1";
30	};
31
32	sram2:memory@20004000 {
33		compatible = "zephyr,memory-region", "mmio-sram";
34		reg = <0x20004000 0x800>;
35		zephyr,memory-region = "SRAM2";
36	};
37
38	soc {
39		flash0:flash@0 {
40			compatible = "soc-nv-flash";
41		};
42
43		/* On-chip EEPROM. */
44		eeprom0: eeprom_0 {
45			compatible = "nxp,lpc11u6x-eeprom";
46			/*
47			 * For some reasons, the IAP commands don't allow to
48			 * reach the last 64 bytes of the EEPROM.
49			 */
50			size = <(DT_SIZE_K(4) - 64)>;
51			status = "okay";
52		};
53
54		iocon: iocon@40044000 {
55			compatible = "nxp,lpc-iocon";
56			reg = <0x40044000 0x150>;
57			#address-cells = <1>;
58			#size-cells = <1>;
59			ranges = <0x0 0x40044000 0x150>;
60			pinctrl: pinctrl {
61				compatible = "nxp,lpc11u6x-pinctrl";
62			};
63			/* PIO0_0 to PIO0_23 */
64			pio0: pio0@0 {
65				compatible = "nxp,lpc-iocon-pio";
66				reg = <0x0 0x60>;
67			};
68			/* PIO1_0 to PIO1_31. */
69			pio1: pio1@60 {
70				compatible = "nxp,lpc-iocon-pio";
71				reg = <0x60 0x7C>;
72			};
73			/* PIO2_0 to PIO2_23. */
74			pio2: pio2@f0 {
75				compatible = "nxp,lpc-iocon-pio";
76				reg = <0xf0 0x60>;
77			};
78		};
79
80		/* GPIO0_0 to GPIO0_23 */
81		gpio0: gpio@0 {
82			compatible = "nxp,lpc11u6x-gpio";
83			reg = <0xa0000000 0x8000>, <0x40048000 0x400>;
84			interrupts = <0 2>, <1 2>, <2 2>, <3 2>, \
85				     <4 2>, <5 2>, <6 2>, <7 2>;
86
87			gpio-controller;
88			#gpio-cells = <2>;
89			ngpios = <24>;
90
91			clocks = <&syscon LPC11U6X_CLOCK_GPIO>;
92			iocon = <&pio0>;
93
94			status = "disabled";
95		};
96
97		/* GPIO1_0 to GPIO1_31 */
98		gpio1: gpio@1 {
99			compatible = "nxp,lpc11u6x-gpio";
100			reg = <0xa0000000 0x8000>, <0x40048000 0x400>;
101			interrupts = <0 2>, <1 2>, <2 2>, <3 2>, \
102				     <4 2>, <5 2>, <6 2>, <7 2>;
103
104			gpio-controller;
105			#gpio-cells = <2>;
106
107			clocks = <&syscon LPC11U6X_CLOCK_GPIO>;
108			iocon = <&pio1>;
109
110			status = "disabled";
111		};
112
113		/* GPIO2_2 to GPIO2_23 */
114		gpio2: gpio@2 {
115			compatible = "nxp,lpc11u6x-gpio";
116			reg = <0xa0000000 0x8000>, <0x40048000 0x400>;
117			interrupts = <0 2>, <1 2>, <2 2>, <3 2>, \
118				     <4 2>, <5 2>, <6 2>, <7 2>;
119
120			gpio-controller;
121			#gpio-cells = <2>;
122			base = <2>;
123			ngpios = <22>;
124
125			clocks = <&syscon LPC11U6X_CLOCK_GPIO>;
126			iocon = <&pio2>;
127
128			status = "disabled";
129		};
130
131		syscon: clock-controller@40048000 {
132			compatible = "nxp,lpc11u6x-syscon";
133			#clock-cells = <1>;
134			reg = <0x40048000 0x400>;
135		};
136
137		uart0: serial@40008000 {
138			compatible = "nxp,lpc11u6x-uart";
139			clocks = <&syscon LPC11U6X_CLOCK_USART0>;
140			interrupts = <21 0>;
141			reg = <0x40008000 0x60>;
142			status = "disabled";
143		};
144
145		uart1: serial@4006c000 {
146			compatible = "nxp,lpc11u6x-uart";
147			clocks = <&syscon LPC11U6X_CLOCK_USART1>;
148			interrupts = <11 0>;
149			reg = <0x4006C000 0x30>;
150			status = "disabled";
151		};
152
153		uart2: serial@40070000 {
154			compatible = "nxp,lpc11u6x-uart";
155			clocks = <&syscon LPC11U6X_CLOCK_USART2>;
156			interrupts = <12 0>;
157			reg = <0x40070000 0x30>;
158			status = "disabled";
159		};
160
161		uart3: serial@40074000 {
162			compatible = "nxp,lpc11u6x-uart";
163			clocks = <&syscon LPC11U6X_CLOCK_USART3>;
164			interrupts = <12 0>;
165			reg = <0x40074000 0x30>;
166			status = "disabled";
167		};
168
169		uart4: serial@4004c000 {
170			compatible = "nxp,lpc11u6x-uart";
171			clocks = <&syscon LPC11U6X_CLOCK_USART4>;
172			interrupts = <11 0>;
173			reg = <0x4004C000 0x30>;
174			status = "disabled";
175		};
176
177		i2c0: i2c@40000000 {
178			compatible = "nxp,lpc11u6x-i2c";
179			#address-cells = <1>;
180			#size-cells = <0>;
181			reg = <0x40000000 0x40>;
182			clocks = <&syscon LPC11U6X_CLOCK_I2C0>;
183			interrupts = <15 0>;
184			status = "disabled";
185		};
186
187		i2c1: i2c@40020000 {
188			compatible = "nxp,lpc11u6x-i2c";
189			#address-cells = <1>;
190			#size-cells = <0>;
191			reg = <0x40020000 0x40>;
192			clocks = <&syscon LPC11U6X_CLOCK_I2C1>;
193			interrupts = <10 0>;
194			status = "disabled";
195		};
196	};
197};
198
199&nvic {
200	arm,num-irq-priority-bits = <2>;
201};
202