1/*
2 * Copyright (c) 2018, Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8
9//#include <zephyr/dt-bindings/i2c/i2c.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11
12#define DT_APB_CLK_HZ	100000000
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu@0 {
20			device_type = "cpu";
21			compatible = "snps,arcem";
22			reg = <0>;
23		};
24	};
25
26	intc: arcv2-intc {
27		compatible = "snps,arcv2-intc";
28		interrupt-controller;
29		#interrupt-cells = <2>;
30	};
31
32	timer0: timer0 {
33		compatible = "snps,arc-timer";
34		interrupts = <16 1>;
35		interrupt-parent = <&intc>;
36	};
37
38	iccm0: iccm@60000000 {
39		compatible = "arc,iccm";
40		reg = <0x60000000 0x20000>;
41	};
42
43	dccm0: dccm@80000000 {
44		compatible = "arc,dccm";
45		reg = <0x80000000 0x20000>;
46	};
47
48	/* this is (Pseudo SRAM), so treat it like mmio-sram */
49	sram0: memory@10000000 {
50		compatible = "mmio-sram";
51		reg = <0x10000000 0x1000000>;
52	};
53
54	spiclk: spi-clock {
55		compatible = "fixed-clock";
56		clock-frequency = <1000000>;
57		#clock-cells = <0>;
58	};
59
60	soc {
61		#address-cells = <1>;
62		#size-cells = <1>;
63		compatible = "simple-bus";
64		ranges;
65
66
67		uart0: uart@f0004000 {
68			compatible = "ns16550";
69			clock-frequency = <DT_APB_CLK_HZ>;
70			reg = <0xf0004000 0x1000>;
71			interrupt-parent = <&intc>;
72			reg-shift = <2>;
73		};
74
75		gpio0: gpio@f0002000 {
76			compatible = "snps,designware-gpio";
77			reg = <0xf0002000 0xc>;
78			ngpios = <4>;
79			interrupt-parent = <&intc>;
80			gpio-controller;
81			#gpio-cells = <2>;
82		};
83
84		gpio1: gpio@f000200c {
85			compatible = "snps,designware-gpio";
86			reg = <0xf000200c 0xc>;
87			ngpios = <8>;
88			gpio-controller;
89			#gpio-cells = <2>;
90		};
91
92		/* wifi rs9113 */
93		spi0: spi@f0008000 {
94			compatible = "snps,designware-spi";
95			reg = <0xf0008000 0x1000>;
96			clocks = <&spiclk>;
97			fifo-depth = <32>;
98			interrupt-parent = <&intc>;
99			#address-cells = <1>;
100			#size-cells = <0>;
101			status = "disabled";
102		};
103
104		pinctrl: pinctrl@f0001000 {
105			compatible = "snps,emsdp-pinctrl";
106			reg = <0xf0001000 0x100>;
107		};
108
109		/* SPI-flash for user data */
110		spi1: spi@f1000000 {
111			compatible = "snps,designware-spi";
112			reg = <0xf1000000 0x1000>;
113			clocks = <&spiclk>;
114			fifo-depth = <32>;
115			interrupt-parent = <&intc>;
116			#address-cells = <1>;
117			#size-cells = <0>;
118			s25fl256s: s25fl256s@0 {
119				compatible = "spansion,s25fl256s", "jedec,spi-nor";
120				reg = <0>;
121				size = <0x10000000>;
122				spi-max-frequency = <100000>;
123				status = "okay";
124				jedec-id = [01 02 19];
125			};
126		};
127
128		/* DFSS-SPI0 */
129		spi2: spi@80010000 {
130			compatible = "snps,designware-spi";
131			#address-cells = <1>;
132			#size-cells = <0>;
133			reg = <0x80010000 0x100>;
134			clocks = <&spiclk>;
135			interrupts = <63 2>, <64 2>, <65 2>;
136			interrupt-names = "err_int", "rx_avail", "tx_req";
137			interrupt-parent = <&intc>;
138			aux_reg;
139			fifo-depth = <16>;
140		};
141
142		/* DFSS-SPI1 */
143		spi3: spi@80010100 {
144			compatible = "snps,designware-spi";
145			#address-cells = <1>;
146			#size-cells = <0>;
147			reg = <0x80010100 0x100>;
148			clocks = <&spiclk>;
149			interrupts = <67 2>, <68 2>, <69 2>;
150			interrupt-names = "err_int", "rx_avail", "tx_req";
151			interrupt-parent = <&intc>;
152			aux_reg;
153			fifo-depth = <16>;
154		};
155	};
156};
157