1 /*
2 * Copyright (C) 2017 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT espressif_esp32_watchdog
8
9 /* Include esp-idf headers first to avoid redefining BIT() macro */
10 #include <soc/rtc_cntl_reg.h>
11 #include <soc/timer_group_reg.h>
12 #include <hal/mwdt_ll.h>
13 #include <hal/wdt_hal.h>
14
15 #include <string.h>
16 #include <zephyr/drivers/watchdog.h>
17 #include <zephyr/drivers/clock_control.h>
18 #ifndef CONFIG_SOC_ESP32C3
19 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
20 #else
21 #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
22 #endif
23 #include <zephyr/device.h>
24
25 #include <zephyr/logging/log.h>
26 LOG_MODULE_REGISTER(wdt_esp32, CONFIG_WDT_LOG_LEVEL);
27
28 #ifdef CONFIG_SOC_ESP32C3
29 #define ISR_HANDLER isr_handler_t
30 #else
31 #define ISR_HANDLER intr_handler_t
32 #endif
33
34 #define MWDT_TICK_PRESCALER 40000
35 #define MWDT_TICKS_PER_US 500
36
37 struct wdt_esp32_data {
38 wdt_hal_context_t hal;
39 uint32_t timeout;
40 wdt_stage_action_t mode;
41 wdt_callback_t callback;
42 };
43
44 struct wdt_esp32_config {
45 wdt_inst_t wdt_inst;
46 const struct device *clock_dev;
47 const clock_control_subsys_t clock_subsys;
48 void (*connect_irq)(void);
49 int irq_source;
50 };
51
wdt_esp32_seal(const struct device * dev)52 static inline void wdt_esp32_seal(const struct device *dev)
53 {
54 struct wdt_esp32_data *data = dev->data;
55
56 wdt_hal_write_protect_enable(&data->hal);
57 }
58
wdt_esp32_unseal(const struct device * dev)59 static inline void wdt_esp32_unseal(const struct device *dev)
60 {
61 struct wdt_esp32_data *data = dev->data;
62
63 wdt_hal_write_protect_disable(&data->hal);
64 }
65
wdt_esp32_enable(const struct device * dev)66 static void wdt_esp32_enable(const struct device *dev)
67 {
68 struct wdt_esp32_data *data = dev->data;
69
70 wdt_esp32_unseal(dev);
71 wdt_hal_enable(&data->hal);
72 wdt_esp32_seal(dev);
73
74 }
75
wdt_esp32_disable(const struct device * dev)76 static int wdt_esp32_disable(const struct device *dev)
77 {
78 struct wdt_esp32_data *data = dev->data;
79
80 wdt_esp32_unseal(dev);
81 wdt_hal_disable(&data->hal);
82 wdt_esp32_seal(dev);
83
84 return 0;
85 }
86
87 static void wdt_esp32_isr(void *arg);
88
wdt_esp32_feed(const struct device * dev,int channel_id)89 static int wdt_esp32_feed(const struct device *dev, int channel_id)
90 {
91 struct wdt_esp32_data *data = dev->data;
92
93 wdt_esp32_unseal(dev);
94 wdt_hal_feed(&data->hal);
95 wdt_esp32_seal(dev);
96
97 return 0;
98 }
99
wdt_esp32_set_config(const struct device * dev,uint8_t options)100 static int wdt_esp32_set_config(const struct device *dev, uint8_t options)
101 {
102 struct wdt_esp32_data *data = dev->data;
103
104 wdt_esp32_unseal(dev);
105 wdt_hal_config_stage(&data->hal, WDT_STAGE0, data->timeout, WDT_STAGE_ACTION_INT);
106 wdt_hal_config_stage(&data->hal, WDT_STAGE1, data->timeout, data->mode);
107 wdt_esp32_enable(dev);
108 wdt_esp32_seal(dev);
109 wdt_esp32_feed(dev, 0);
110
111 return 0;
112 }
113
wdt_esp32_install_timeout(const struct device * dev,const struct wdt_timeout_cfg * cfg)114 static int wdt_esp32_install_timeout(const struct device *dev,
115 const struct wdt_timeout_cfg *cfg)
116 {
117 struct wdt_esp32_data *data = dev->data;
118
119 if (cfg->window.min != 0U || cfg->window.max == 0U) {
120 return -EINVAL;
121 }
122
123 data->timeout = cfg->window.max;
124 data->callback = cfg->callback;
125
126 /* Set mode of watchdog and callback */
127 switch (cfg->flags) {
128 case WDT_FLAG_RESET_SOC:
129 data->mode = WDT_STAGE_ACTION_RESET_SYSTEM;
130 LOG_DBG("Configuring reset SOC mode");
131 break;
132
133 case WDT_FLAG_RESET_CPU_CORE:
134 data->mode = WDT_STAGE_ACTION_RESET_CPU;
135 LOG_DBG("Configuring reset CPU mode");
136 break;
137
138 case WDT_FLAG_RESET_NONE:
139 data->mode = WDT_STAGE_ACTION_OFF;
140 LOG_DBG("Configuring non-reset mode");
141 break;
142
143 default:
144 LOG_ERR("Unsupported watchdog config flag");
145 return -EINVAL;
146 }
147
148 return 0;
149 }
150
wdt_esp32_init(const struct device * dev)151 static int wdt_esp32_init(const struct device *dev)
152 {
153 const struct wdt_esp32_config *const config = dev->config;
154 struct wdt_esp32_data *data = dev->data;
155
156 if (!device_is_ready(config->clock_dev)) {
157 LOG_ERR("clock control device not ready");
158 return -ENODEV;
159 }
160
161 clock_control_on(config->clock_dev, config->clock_subsys);
162
163 wdt_hal_init(&data->hal, config->wdt_inst, MWDT_TICK_PRESCALER, true);
164
165 esp_intr_alloc(config->irq_source,
166 0,
167 (ISR_HANDLER)wdt_esp32_isr,
168 (void *)dev,
169 NULL);
170
171 #ifndef CONFIG_WDT_DISABLE_AT_BOOT
172 wdt_esp32_enable(dev);
173 #endif
174
175 return 0;
176 }
177
178 static const struct wdt_driver_api wdt_api = {
179 .setup = wdt_esp32_set_config,
180 .disable = wdt_esp32_disable,
181 .install_timeout = wdt_esp32_install_timeout,
182 .feed = wdt_esp32_feed
183 };
184
185 #define ESP32_WDT_INIT(idx) \
186 static struct wdt_esp32_data wdt##idx##_data; \
187 static struct wdt_esp32_config wdt_esp32_config##idx = { \
188 .wdt_inst = WDT_MWDT##idx, \
189 .irq_source = DT_IRQN(DT_NODELABEL(wdt##idx)), \
190 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
191 .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
192 }; \
193 \
194 DEVICE_DT_INST_DEFINE(idx, \
195 wdt_esp32_init, \
196 NULL, \
197 &wdt##idx##_data, \
198 &wdt_esp32_config##idx, \
199 PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
200 &wdt_api)
201
wdt_esp32_isr(void * arg)202 static void wdt_esp32_isr(void *arg)
203 {
204 const struct device *dev = (const struct device *)arg;
205 const struct wdt_esp32_config *config = dev->config;
206 struct wdt_esp32_data *data = dev->data;
207
208 if (data->callback) {
209 data->callback(dev, 0);
210 }
211
212 wdt_hal_handle_intr(&data->hal);
213 }
214
215
216 #if DT_NODE_HAS_STATUS(DT_NODELABEL(wdt0), okay)
217 ESP32_WDT_INIT(0);
218 #endif
219
220 #if DT_NODE_HAS_STATUS(DT_NODELABEL(wdt1), okay)
221 ESP32_WDT_INIT(1);
222 #endif
223
