1 /* ns16550.c - NS16550D serial driver */
2
3 #define DT_DRV_COMPAT ns16550
4
5 /*
6 * Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
7 * Copyright (c) 2020-2022 Intel Corp.
8 *
9 * SPDX-License-Identifier: Apache-2.0
10 */
11
12 /**
13 * @brief NS16550 Serial Driver
14 *
15 * This is the driver for the Intel NS16550 UART Chip used on the PC 386.
16 * It uses the SCCs in asynchronous mode only.
17 *
18 * Before individual UART port can be used, uart_ns16550_port_init() has to be
19 * called to setup the port.
20 */
21
22 #include <errno.h>
23 #include <zephyr/kernel.h>
24 #include <zephyr/arch/cpu.h>
25 #include <zephyr/types.h>
26
27 #include <zephyr/init.h>
28 #include <zephyr/toolchain.h>
29 #include <zephyr/linker/sections.h>
30 #include <zephyr/drivers/uart.h>
31 #include <zephyr/drivers/clock_control.h>
32 #include <zephyr/pm/policy.h>
33 #include <zephyr/sys/sys_io.h>
34 #include <zephyr/spinlock.h>
35 #include <zephyr/irq.h>
36
37 #if defined(CONFIG_PINCTRL)
38 #include <zephyr/drivers/pinctrl.h>
39 #endif
40
41 #include <zephyr/drivers/serial/uart_ns16550.h>
42
43 #define INST_HAS_PCP_HELPER(inst) DT_INST_NODE_HAS_PROP(inst, pcp) ||
44 #define INST_HAS_DLF_HELPER(inst) DT_INST_NODE_HAS_PROP(inst, dlf) ||
45
46 #define UART_NS16550_PCP_ENABLED \
47 (DT_INST_FOREACH_STATUS_OKAY(INST_HAS_PCP_HELPER) 0)
48 #define UART_NS16550_DLF_ENABLED \
49 (DT_INST_FOREACH_STATUS_OKAY(INST_HAS_DLF_HELPER) 0)
50
51 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
52 BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
53 #include <zephyr/drivers/pcie/pcie.h>
54 #endif
55
56 /* register definitions */
57
58 #define REG_THR 0x00 /* Transmitter holding reg. */
59 #define REG_RDR 0x00 /* Receiver data reg. */
60 #define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
61 #define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
62 #define REG_IER 0x01 /* Interrupt enable reg. */
63 #define REG_IIR 0x02 /* Interrupt ID reg. */
64 #define REG_FCR 0x02 /* FIFO control reg. */
65 #define REG_LCR 0x03 /* Line control reg. */
66 #define REG_MDC 0x04 /* Modem control reg. */
67 #define REG_LSR 0x05 /* Line status reg. */
68 #define REG_MSR 0x06 /* Modem status reg. */
69 #define REG_DLF 0xC0 /* Divisor Latch Fraction */
70 #define REG_PCP 0x200 /* PRV_CLOCK_PARAMS (Apollo Lake) */
71
72 /* equates for interrupt enable register */
73
74 #define IER_RXRDY 0x01 /* receiver data ready */
75 #define IER_TBE 0x02 /* transmit bit enable */
76 #define IER_LSR 0x04 /* line status interrupts */
77 #define IER_MSI 0x08 /* modem status interrupts */
78
79 /* equates for interrupt identification register */
80
81 #define IIR_MSTAT 0x00 /* modem status interrupt */
82 #define IIR_NIP 0x01 /* no interrupt pending */
83 #define IIR_THRE 0x02 /* transmit holding register empty interrupt */
84 #define IIR_RBRF 0x04 /* receiver buffer register full interrupt */
85 #define IIR_LS 0x06 /* receiver line status interrupt */
86 #define IIR_MASK 0x07 /* interrupt id bits mask */
87 #define IIR_ID 0x06 /* interrupt ID mask without NIP */
88 #define IIR_FE 0xC0 /* FIFO mode enabled */
89 #define IIR_CH 0x0C /* Character timeout*/
90
91 /* equates for FIFO control register */
92
93 #define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */
94 #define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */
95 #define FCR_XMITCLR 0x04 /* clear XMIT FIFO */
96
97 /* equates for Apollo Lake clock control register (PRV_CLOCK_PARAMS) */
98
99 #define PCP_UPDATE 0x80000000 /* update clock */
100 #define PCP_EN 0x00000001 /* enable clock output */
101
102 /*
103 * Per PC16550D (Literature Number: SNLS378B):
104 *
105 * RXRDY, Mode 0: When in the 16450 Mode (FCR0 = 0) or in
106 * the FIFO Mode (FCR0 = 1, FCR3 = 0) and there is at least 1
107 * character in the RCVR FIFO or RCVR holding register, the
108 * RXRDY pin (29) will be low active. Once it is activated the
109 * RXRDY pin will go inactive when there are no more charac-
110 * ters in the FIFO or holding register.
111 *
112 * RXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when the
113 * FCR3 = 1 and the trigger level or the timeout has been
114 * reached, the RXRDY pin will go low active. Once it is acti-
115 * vated it will go inactive when there are no more characters
116 * in the FIFO or holding register.
117 *
118 * TXRDY, Mode 0: In the 16450 Mode (FCR0 = 0) or in the
119 * FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
120 * ters in the XMIT FIFO or XMIT holding register, the TXRDY
121 * pin (24) will be low active. Once it is activated the TXRDY
122 * pin will go inactive after the first character is loaded into the
123 * XMIT FIFO or holding register.
124 *
125 * TXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when
126 * FCR3 = 1 and there are no characters in the XMIT FIFO, the
127 * TXRDY pin will go low active. This pin will become inactive
128 * when the XMIT FIFO is completely full.
129 */
130 #define FCR_MODE0 0x00 /* set receiver in mode 0 */
131 #define FCR_MODE1 0x08 /* set receiver in mode 1 */
132
133 /* RCVR FIFO interrupt levels: trigger interrupt with this bytes in FIFO */
134 #define FCR_FIFO_1 0x00 /* 1 byte in RCVR FIFO */
135 #define FCR_FIFO_4 0x40 /* 4 bytes in RCVR FIFO */
136 #define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */
137 #define FCR_FIFO_14 0xC0 /* 14 bytes in RCVR FIFO */
138
139 /*
140 * UART NS16750 supports 64 bytes FIFO, which can be enabled
141 * via the FCR register
142 */
143 #define FCR_FIFO_64 0x20 /* Enable 64 bytes FIFO */
144
145 /* constants for line control register */
146
147 #define LCR_CS5 0x00 /* 5 bits data size */
148 #define LCR_CS6 0x01 /* 6 bits data size */
149 #define LCR_CS7 0x02 /* 7 bits data size */
150 #define LCR_CS8 0x03 /* 8 bits data size */
151 #define LCR_2_STB 0x04 /* 2 stop bits */
152 #define LCR_1_STB 0x00 /* 1 stop bit */
153 #define LCR_PEN 0x08 /* parity enable */
154 #define LCR_PDIS 0x00 /* parity disable */
155 #define LCR_EPS 0x10 /* even parity select */
156 #define LCR_SP 0x20 /* stick parity select */
157 #define LCR_SBRK 0x40 /* break control bit */
158 #define LCR_DLAB 0x80 /* divisor latch access enable */
159
160 /* constants for the modem control register */
161
162 #define MCR_DTR 0x01 /* dtr output */
163 #define MCR_RTS 0x02 /* rts output */
164 #define MCR_OUT1 0x04 /* output #1 */
165 #define MCR_OUT2 0x08 /* output #2 */
166 #define MCR_LOOP 0x10 /* loop back */
167 #define MCR_AFCE 0x20 /* auto flow control enable */
168
169 /* constants for line status register */
170
171 #define LSR_RXRDY 0x01 /* receiver data available */
172 #define LSR_OE 0x02 /* overrun error */
173 #define LSR_PE 0x04 /* parity error */
174 #define LSR_FE 0x08 /* framing error */
175 #define LSR_BI 0x10 /* break interrupt */
176 #define LSR_EOB_MASK 0x1E /* Error or Break mask */
177 #define LSR_THRE 0x20 /* transmit holding register empty */
178 #define LSR_TEMT 0x40 /* transmitter empty */
179
180 /* constants for modem status register */
181
182 #define MSR_DCTS 0x01 /* cts change */
183 #define MSR_DDSR 0x02 /* dsr change */
184 #define MSR_DRI 0x04 /* ring change */
185 #define MSR_DDCD 0x08 /* data carrier change */
186 #define MSR_CTS 0x10 /* complement of cts */
187 #define MSR_DSR 0x20 /* complement of dsr */
188 #define MSR_RI 0x40 /* complement of ring signal */
189 #define MSR_DCD 0x80 /* complement of dcd */
190
191 #define THR(dev) (get_port(dev) + REG_THR * reg_interval(dev))
192 #define RDR(dev) (get_port(dev) + REG_RDR * reg_interval(dev))
193 #define BRDL(dev) (get_port(dev) + REG_BRDL * reg_interval(dev))
194 #define BRDH(dev) (get_port(dev) + REG_BRDH * reg_interval(dev))
195 #define IER(dev) (get_port(dev) + REG_IER * reg_interval(dev))
196 #define IIR(dev) (get_port(dev) + REG_IIR * reg_interval(dev))
197 #define FCR(dev) (get_port(dev) + REG_FCR * reg_interval(dev))
198 #define LCR(dev) (get_port(dev) + REG_LCR * reg_interval(dev))
199 #define MDC(dev) (get_port(dev) + REG_MDC * reg_interval(dev))
200 #define LSR(dev) (get_port(dev) + REG_LSR * reg_interval(dev))
201 #define MSR(dev) (get_port(dev) + REG_MSR * reg_interval(dev))
202 #define DLF(dev) (get_port(dev) + REG_DLF)
203 #define PCP(dev) (get_port(dev) + REG_PCP)
204
205 #define IIRC(dev) (((struct uart_ns16550_dev_data *)(dev)->data)->iir_cache)
206
207 /* device config */
208 struct uart_ns16550_device_config {
209 union {
210 DEVICE_MMIO_ROM;
211 uint32_t port;
212 };
213 uint32_t sys_clk_freq;
214 const struct device *clock_dev;
215 clock_control_subsys_t clock_subsys;
216 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
217 uart_irq_config_func_t irq_config_func;
218 #endif
219 #if UART_NS16550_PCP_ENABLED
220 uint32_t pcp;
221 #endif
222 uint8_t reg_interval;
223 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
224 struct pcie_dev *pcie;
225 #endif
226 #if defined(CONFIG_PINCTRL)
227 const struct pinctrl_dev_config *pincfg;
228 #endif
229 #if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
230 bool io_map;
231 #endif
232 };
233
234 /** Device data structure */
235 struct uart_ns16550_dev_data {
236 DEVICE_MMIO_RAM;
237 struct uart_config uart_config;
238 struct k_spinlock lock;
239 uint8_t fifo_size;
240
241 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
242 uint8_t iir_cache; /**< cache of IIR since it clears when read */
243 uart_irq_callback_user_data_t cb; /**< Callback function pointer */
244 void *cb_data; /**< Callback function arg */
245 #endif
246
247 #if UART_NS16550_DLF_ENABLED
248 uint8_t dlf; /**< DLF value */
249 #endif
250
251 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
252 bool tx_stream_on;
253 #endif
254 };
255
ns16550_outbyte(const struct uart_ns16550_device_config * cfg,uintptr_t port,uint8_t val)256 static void ns16550_outbyte(const struct uart_ns16550_device_config *cfg,
257 uintptr_t port, uint8_t val)
258 {
259 #if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
260 if (cfg->io_map) {
261 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
262 sys_out32(val, port);
263 } else {
264 sys_out8(val, port);
265 }
266 } else {
267 #else
268 {
269 #endif
270 /* MMIO mapped */
271 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
272 sys_write32(val, port);
273 } else {
274 sys_write8(val, port);
275 }
276 }
277 }
278
279 static uint8_t ns16550_inbyte(const struct uart_ns16550_device_config *cfg,
280 uintptr_t port)
281 {
282 #if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
283 if (cfg->io_map) {
284 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
285 return sys_in32(port);
286 } else {
287 return sys_in8(port);
288 }
289 } else {
290 #else
291 {
292 #endif
293 /* MMIO mapped */
294 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
295 return sys_read32(port);
296 } else {
297 return sys_read8(port);
298 }
299 }
300 return 0;
301 }
302
303 #if UART_NS16550_PCP_ENABLED
304 static void ns16550_outword(const struct uart_ns16550_device_config *cfg,
305 uintptr_t port, uint32_t val)
306 {
307 #if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
308 if (cfg->io_map) {
309 sys_out32(val, port);
310 } else {
311 #else
312 {
313 #endif
314 /* MMIO mapped */
315 sys_write32(val, port);
316 }
317 }
318
319 static uint32_t ns16550_inword(const struct uart_ns16550_device_config *cfg,
320 uintptr_t port)
321 {
322 #if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
323 if (cfg->io_map) {
324 return sys_in32(port);
325 }
326 #endif
327 /* MMIO mapped */
328 return sys_read32(port);
329 }
330 #endif
331
332 static inline uint8_t reg_interval(const struct device *dev)
333 {
334 const struct uart_ns16550_device_config *config = dev->config;
335
336 return config->reg_interval;
337 }
338
339 static const struct uart_driver_api uart_ns16550_driver_api;
340
341 static inline uintptr_t get_port(const struct device *dev)
342 {
343 uintptr_t port;
344 #if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
345 const struct uart_ns16550_device_config *config = dev->config;
346
347 if (config->io_map) {
348 port = config->port;
349 } else {
350 #else
351 {
352 #endif
353 port = DEVICE_MMIO_GET(dev);
354 }
355
356 return port;
357 }
358
359 static void set_baud_rate(const struct device *dev, uint32_t baud_rate, uint32_t pclk)
360 {
361 struct uart_ns16550_dev_data * const dev_data = dev->data;
362 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
363 uint32_t divisor; /* baud rate divisor */
364 uint8_t lcr_cache;
365
366 if ((baud_rate != 0U) && (pclk != 0U)) {
367 /*
368 * calculate baud rate divisor. a variant of
369 * (uint32_t)(pclk / (16.0 * baud_rate) + 0.5)
370 */
371 divisor = ((pclk + (baud_rate << 3))
372 / baud_rate) >> 4;
373
374 /* set the DLAB to access the baud rate divisor registers */
375 lcr_cache = ns16550_inbyte(dev_cfg, LCR(dev));
376 ns16550_outbyte(dev_cfg, LCR(dev), LCR_DLAB | lcr_cache);
377 ns16550_outbyte(dev_cfg, BRDL(dev), (unsigned char)(divisor & 0xff));
378 ns16550_outbyte(dev_cfg, BRDH(dev), (unsigned char)((divisor >> 8) & 0xff));
379
380 /* restore the DLAB to access the baud rate divisor registers */
381 ns16550_outbyte(dev_cfg, LCR(dev), lcr_cache);
382
383 dev_data->uart_config.baudrate = baud_rate;
384 }
385 }
386
387 static int uart_ns16550_configure(const struct device *dev,
388 const struct uart_config *cfg)
389 {
390 struct uart_ns16550_dev_data * const dev_data = dev->data;
391 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
392 uint8_t mdc = 0U;
393 uint32_t pclk = 0U;
394
395 /* temp for return value if error occurs in this locked region */
396 int ret = 0;
397
398 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
399
400 #if defined(CONFIG_PINCTRL)
401 if (dev_cfg->pincfg != NULL) {
402 pinctrl_apply_state(dev_cfg->pincfg, PINCTRL_STATE_DEFAULT);
403 }
404 #endif
405
406 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
407 dev_data->iir_cache = 0U;
408 #endif
409
410 #if UART_NS16550_DLF_ENABLED
411 ns16550_outbyte(dev_cfg, DLF(dev), dev_data->dlf);
412 #endif
413
414 #if UART_NS16550_PCP_ENABLED
415 uint32_t pcp = dev_cfg->pcp;
416
417 if (pcp) {
418 pcp |= PCP_EN;
419 ns16550_outbyte(dev_cfg, PCP(dev), pcp & ~PCP_UPDATE);
420 ns16550_outbyte(dev_cfg, PCP(dev), pcp | PCP_UPDATE);
421 }
422 #endif
423
424 /*
425 * set clock frequency from clock_frequency property if valid,
426 * otherwise, get clock frequency from clock manager
427 */
428 if (dev_cfg->sys_clk_freq != 0U) {
429 pclk = dev_cfg->sys_clk_freq;
430 } else {
431 if (!device_is_ready(dev_cfg->clock_dev)) {
432 ret = -EINVAL;
433 goto out;
434 }
435
436 clock_control_get_rate(dev_cfg->clock_dev, dev_cfg->clock_subsys,
437 &pclk);
438 }
439
440 set_baud_rate(dev, cfg->baudrate, pclk);
441
442 /* Local structure to hold temporary values to pass to ns16550_outbyte() */
443 struct uart_config uart_cfg;
444
445 switch (cfg->data_bits) {
446 case UART_CFG_DATA_BITS_5:
447 uart_cfg.data_bits = LCR_CS5;
448 break;
449 case UART_CFG_DATA_BITS_6:
450 uart_cfg.data_bits = LCR_CS6;
451 break;
452 case UART_CFG_DATA_BITS_7:
453 uart_cfg.data_bits = LCR_CS7;
454 break;
455 case UART_CFG_DATA_BITS_8:
456 uart_cfg.data_bits = LCR_CS8;
457 break;
458 default:
459 ret = -ENOTSUP;
460 goto out;
461 }
462
463 switch (cfg->stop_bits) {
464 case UART_CFG_STOP_BITS_1:
465 uart_cfg.stop_bits = LCR_1_STB;
466 break;
467 case UART_CFG_STOP_BITS_2:
468 uart_cfg.stop_bits = LCR_2_STB;
469 break;
470 default:
471 ret = -ENOTSUP;
472 goto out;
473 }
474
475 switch (cfg->parity) {
476 case UART_CFG_PARITY_NONE:
477 uart_cfg.parity = LCR_PDIS;
478 break;
479 case UART_CFG_PARITY_EVEN:
480 uart_cfg.parity = LCR_EPS;
481 break;
482 default:
483 ret = -ENOTSUP;
484 goto out;
485 }
486
487 dev_data->uart_config = *cfg;
488
489 /* data bits, stop bits, parity, clear DLAB */
490 ns16550_outbyte(dev_cfg, LCR(dev),
491 uart_cfg.data_bits | uart_cfg.stop_bits | uart_cfg.parity);
492
493 mdc = MCR_OUT2 | MCR_RTS | MCR_DTR;
494 #if defined(CONFIG_UART_NS16550_VARIANT_NS16750) || \
495 defined(CONFIG_UART_NS16550_VARIANT_NS16950)
496 if (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS) {
497 mdc |= MCR_AFCE;
498 }
499 #endif
500
501 ns16550_outbyte(dev_cfg, MDC(dev), mdc);
502
503 /*
504 * Program FIFO: enabled, mode 0 (set for compatibility with quark),
505 * generate the interrupt at 8th byte
506 * Clear TX and RX FIFO
507 */
508 ns16550_outbyte(dev_cfg, FCR(dev),
509 FCR_FIFO | FCR_MODE0 | FCR_FIFO_8 | FCR_RCVRCLR | FCR_XMITCLR
510 #ifdef CONFIG_UART_NS16550_VARIANT_NS16750
511 | FCR_FIFO_64
512 #endif
513 );
514
515 if ((ns16550_inbyte(dev_cfg, IIR(dev)) & IIR_FE) == IIR_FE) {
516 #ifdef CONFIG_UART_NS16550_VARIANT_NS16750
517 dev_data->fifo_size = 64;
518 #elif defined(CONFIG_UART_NS16550_VARIANT_NS16950)
519 dev_data->fifo_size = 128;
520 #else
521 dev_data->fifo_size = 16;
522 #endif
523 } else {
524 dev_data->fifo_size = 1;
525 }
526
527 /* clear the port */
528 ns16550_inbyte(dev_cfg, RDR(dev));
529
530 /* disable interrupts */
531 ns16550_outbyte(dev_cfg, IER(dev), 0x00);
532
533 out:
534 k_spin_unlock(&dev_data->lock, key);
535 return ret;
536 };
537
538 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
539 static int uart_ns16550_config_get(const struct device *dev,
540 struct uart_config *cfg)
541 {
542 struct uart_ns16550_dev_data *data = dev->data;
543
544 cfg->baudrate = data->uart_config.baudrate;
545 cfg->parity = data->uart_config.parity;
546 cfg->stop_bits = data->uart_config.stop_bits;
547 cfg->data_bits = data->uart_config.data_bits;
548 cfg->flow_ctrl = data->uart_config.flow_ctrl;
549
550 return 0;
551 }
552 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
553
554 /**
555 * @brief Initialize individual UART port
556 *
557 * This routine is called to reset the chip in a quiescent state.
558 *
559 * @param dev UART device struct
560 *
561 * @return 0 if successful, failed otherwise
562 */
563 static int uart_ns16550_init(const struct device *dev)
564 {
565 struct uart_ns16550_dev_data *data = dev->data;
566 const struct uart_ns16550_device_config *dev_cfg = dev->config;
567 int ret;
568
569 ARG_UNUSED(dev_cfg);
570
571 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
572 if (dev_cfg->pcie) {
573 struct pcie_bar mbar;
574
575 if (dev_cfg->pcie->bdf == PCIE_BDF_NONE) {
576 return -EINVAL;
577 }
578
579 pcie_probe_mbar(dev_cfg->pcie->bdf, 0, &mbar);
580 pcie_set_cmd(dev_cfg->pcie->bdf, PCIE_CONF_CMDSTAT_MEM, true);
581
582 device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr, mbar.size,
583 K_MEM_CACHE_NONE);
584 } else
585 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) */
586 {
587 #if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
588 /* Map directly from DTS */
589 if (!dev_cfg->io_map) {
590 #else
591 {
592 #endif
593 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
594 }
595 }
596
597 ret = uart_ns16550_configure(dev, &data->uart_config);
598 if (ret != 0) {
599 return ret;
600 }
601
602 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
603 dev_cfg->irq_config_func(dev);
604 #endif
605
606 return 0;
607 }
608
609 /**
610 * @brief Poll the device for input.
611 *
612 * @param dev UART device struct
613 * @param c Pointer to character
614 *
615 * @return 0 if a character arrived, -1 if the input buffer if empty.
616 */
617 static int uart_ns16550_poll_in(const struct device *dev, unsigned char *c)
618 {
619 struct uart_ns16550_dev_data *data = dev->data;
620 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
621 int ret = -1;
622 k_spinlock_key_t key = k_spin_lock(&data->lock);
623
624 if ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_RXRDY) != 0) {
625 /* got a character */
626 *c = ns16550_inbyte(dev_cfg, RDR(dev));
627 ret = 0;
628 }
629
630 k_spin_unlock(&data->lock, key);
631
632 return ret;
633 }
634
635 /**
636 * @brief Output a character in polled mode.
637 *
638 * Checks if the transmitter is empty. If empty, a character is written to
639 * the data register.
640 *
641 * If the hardware flow control is enabled then the handshake signal CTS has to
642 * be asserted in order to send a character.
643 *
644 * @param dev UART device struct
645 * @param c Character to send
646 */
647 static void uart_ns16550_poll_out(const struct device *dev,
648 unsigned char c)
649 {
650 struct uart_ns16550_dev_data *data = dev->data;
651 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
652 k_spinlock_key_t key = k_spin_lock(&data->lock);
653
654 while ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_THRE) == 0) {
655 }
656
657 ns16550_outbyte(dev_cfg, THR(dev), c);
658
659 k_spin_unlock(&data->lock, key);
660 }
661
662 /**
663 * @brief Check if an error was received
664 *
665 * @param dev UART device struct
666 *
667 * @return one of UART_ERROR_OVERRUN, UART_ERROR_PARITY, UART_ERROR_FRAMING,
668 * UART_BREAK if an error was detected, 0 otherwise.
669 */
670 static int uart_ns16550_err_check(const struct device *dev)
671 {
672 struct uart_ns16550_dev_data *data = dev->data;
673 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
674 k_spinlock_key_t key = k_spin_lock(&data->lock);
675 int check = (ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_EOB_MASK);
676
677 k_spin_unlock(&data->lock, key);
678
679 return check >> 1;
680 }
681
682 #if CONFIG_UART_INTERRUPT_DRIVEN
683
684 /**
685 * @brief Fill FIFO with data
686 *
687 * @param dev UART device struct
688 * @param tx_data Data to transmit
689 * @param size Number of bytes to send
690 *
691 * @return Number of bytes sent
692 */
693 static int uart_ns16550_fifo_fill(const struct device *dev,
694 const uint8_t *tx_data,
695 int size)
696 {
697 struct uart_ns16550_dev_data *data = dev->data;
698 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
699 int i;
700 k_spinlock_key_t key = k_spin_lock(&data->lock);
701
702 for (i = 0; (i < size) && (i < data->fifo_size); i++) {
703 ns16550_outbyte(dev_cfg, THR(dev), tx_data[i]);
704 }
705
706 k_spin_unlock(&data->lock, key);
707
708 return i;
709 }
710
711 /**
712 * @brief Read data from FIFO
713 *
714 * @param dev UART device struct
715 * @param rxData Data container
716 * @param size Container size
717 *
718 * @return Number of bytes read
719 */
720 static int uart_ns16550_fifo_read(const struct device *dev, uint8_t *rx_data,
721 const int size)
722 {
723 struct uart_ns16550_dev_data *data = dev->data;
724 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
725 int i;
726 k_spinlock_key_t key = k_spin_lock(&data->lock);
727
728 for (i = 0; (i < size) && (ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_RXRDY) != 0; i++) {
729 rx_data[i] = ns16550_inbyte(dev_cfg, RDR(dev));
730 }
731
732 k_spin_unlock(&data->lock, key);
733
734 return i;
735 }
736
737 /**
738 * @brief Enable TX interrupt in IER
739 *
740 * @param dev UART device struct
741 */
742 static void uart_ns16550_irq_tx_enable(const struct device *dev)
743 {
744 struct uart_ns16550_dev_data *data = dev->data;
745 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
746 k_spinlock_key_t key = k_spin_lock(&data->lock);
747
748 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
749 struct uart_ns16550_dev_data *const dev_data = dev->data;
750
751 if (!dev_data->tx_stream_on) {
752 dev_data->tx_stream_on = true;
753 uint8_t num_cpu_states;
754 const struct pm_state_info *cpu_states;
755
756 num_cpu_states = pm_state_cpu_get_all(0U, &cpu_states);
757
758 /*
759 * Power state to be disabled. Some platforms have multiple
760 * states and need to be given a constraint set according to
761 * different states.
762 */
763 for (uint8_t i = 0U; i < num_cpu_states; i++) {
764 pm_policy_state_lock_get(cpu_states[i].state, PM_ALL_SUBSTATES);
765 }
766 }
767 #endif
768 ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) | IER_TBE);
769
770 k_spin_unlock(&data->lock, key);
771 }
772
773 /**
774 * @brief Disable TX interrupt in IER
775 *
776 * @param dev UART device struct
777 */
778 static void uart_ns16550_irq_tx_disable(const struct device *dev)
779 {
780 struct uart_ns16550_dev_data *data = dev->data;
781 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
782 k_spinlock_key_t key = k_spin_lock(&data->lock);
783
784 ns16550_outbyte(dev_cfg, IER(dev),
785 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_TBE));
786
787 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
788 struct uart_ns16550_dev_data *const dev_data = dev->data;
789
790 if (dev_data->tx_stream_on) {
791 dev_data->tx_stream_on = false;
792 uint8_t num_cpu_states;
793 const struct pm_state_info *cpu_states;
794
795 num_cpu_states = pm_state_cpu_get_all(0U, &cpu_states);
796
797 /*
798 * Power state to be enabled. Some platforms have multiple
799 * states and need to be given a constraint release according
800 * to different states.
801 */
802 for (uint8_t i = 0U; i < num_cpu_states; i++) {
803 pm_policy_state_lock_put(cpu_states[i].state, PM_ALL_SUBSTATES);
804 }
805 }
806 #endif
807 k_spin_unlock(&data->lock, key);
808 }
809
810 /**
811 * @brief Check if Tx IRQ has been raised
812 *
813 * @param dev UART device struct
814 *
815 * @return 1 if an IRQ is ready, 0 otherwise
816 */
817 static int uart_ns16550_irq_tx_ready(const struct device *dev)
818 {
819 struct uart_ns16550_dev_data *data = dev->data;
820 k_spinlock_key_t key = k_spin_lock(&data->lock);
821
822 int ret = ((IIRC(dev) & IIR_ID) == IIR_THRE) ? 1 : 0;
823
824 k_spin_unlock(&data->lock, key);
825
826 return ret;
827 }
828
829 /**
830 * @brief Check if nothing remains to be transmitted
831 *
832 * @param dev UART device struct
833 *
834 * @return 1 if nothing remains to be transmitted, 0 otherwise
835 */
836 static int uart_ns16550_irq_tx_complete(const struct device *dev)
837 {
838 struct uart_ns16550_dev_data *data = dev->data;
839 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
840 k_spinlock_key_t key = k_spin_lock(&data->lock);
841
842 int ret = ((ns16550_inbyte(dev_cfg, LSR(dev)) & (LSR_TEMT | LSR_THRE))
843 == (LSR_TEMT | LSR_THRE)) ? 1 : 0;
844
845 k_spin_unlock(&data->lock, key);
846
847 return ret;
848 }
849
850 /**
851 * @brief Enable RX interrupt in IER
852 *
853 * @param dev UART device struct
854 */
855 static void uart_ns16550_irq_rx_enable(const struct device *dev)
856 {
857 struct uart_ns16550_dev_data *data = dev->data;
858 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
859 k_spinlock_key_t key = k_spin_lock(&data->lock);
860
861 ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) | IER_RXRDY);
862
863 k_spin_unlock(&data->lock, key);
864 }
865
866 /**
867 * @brief Disable RX interrupt in IER
868 *
869 * @param dev UART device struct
870 */
871 static void uart_ns16550_irq_rx_disable(const struct device *dev)
872 {
873 struct uart_ns16550_dev_data *data = dev->data;
874 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
875 k_spinlock_key_t key = k_spin_lock(&data->lock);
876
877 ns16550_outbyte(dev_cfg, IER(dev),
878 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_RXRDY));
879
880 k_spin_unlock(&data->lock, key);
881 }
882
883 /**
884 * @brief Check if Rx IRQ has been raised
885 *
886 * @param dev UART device struct
887 *
888 * @return 1 if an IRQ is ready, 0 otherwise
889 */
890 static int uart_ns16550_irq_rx_ready(const struct device *dev)
891 {
892 struct uart_ns16550_dev_data *data = dev->data;
893 k_spinlock_key_t key = k_spin_lock(&data->lock);
894
895 int ret = ((IIRC(dev) & IIR_ID) == IIR_RBRF) ? 1 : 0;
896
897 k_spin_unlock(&data->lock, key);
898
899 return ret;
900 }
901
902 /**
903 * @brief Enable error interrupt in IER
904 *
905 * @param dev UART device struct
906 */
907 static void uart_ns16550_irq_err_enable(const struct device *dev)
908 {
909 struct uart_ns16550_dev_data *data = dev->data;
910 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
911 k_spinlock_key_t key = k_spin_lock(&data->lock);
912
913 ns16550_outbyte(dev_cfg, IER(dev),
914 ns16550_inbyte(dev_cfg, IER(dev)) | IER_LSR);
915
916 k_spin_unlock(&data->lock, key);
917 }
918
919 /**
920 * @brief Disable error interrupt in IER
921 *
922 * @param dev UART device struct
923 *
924 * @return 1 if an IRQ is ready, 0 otherwise
925 */
926 static void uart_ns16550_irq_err_disable(const struct device *dev)
927 {
928 struct uart_ns16550_dev_data *data = dev->data;
929 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
930 k_spinlock_key_t key = k_spin_lock(&data->lock);
931
932 ns16550_outbyte(dev_cfg, IER(dev),
933 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_LSR));
934
935 k_spin_unlock(&data->lock, key);
936 }
937
938 /**
939 * @brief Check if any IRQ is pending
940 *
941 * @param dev UART device struct
942 *
943 * @return 1 if an IRQ is pending, 0 otherwise
944 */
945 static int uart_ns16550_irq_is_pending(const struct device *dev)
946 {
947 struct uart_ns16550_dev_data *data = dev->data;
948 k_spinlock_key_t key = k_spin_lock(&data->lock);
949
950 int ret = (!(IIRC(dev) & IIR_NIP)) ? 1 : 0;
951
952 k_spin_unlock(&data->lock, key);
953
954 return ret;
955 }
956
957 /**
958 * @brief Update cached contents of IIR
959 *
960 * @param dev UART device struct
961 *
962 * @return Always 1
963 */
964 static int uart_ns16550_irq_update(const struct device *dev)
965 {
966 struct uart_ns16550_dev_data *data = dev->data;
967 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
968 k_spinlock_key_t key = k_spin_lock(&data->lock);
969
970 IIRC(dev) = ns16550_inbyte(dev_cfg, IIR(dev));
971
972 k_spin_unlock(&data->lock, key);
973
974 return 1;
975 }
976
977 /**
978 * @brief Set the callback function pointer for IRQ.
979 *
980 * @param dev UART device struct
981 * @param cb Callback function pointer.
982 */
983 static void uart_ns16550_irq_callback_set(const struct device *dev,
984 uart_irq_callback_user_data_t cb,
985 void *cb_data)
986 {
987 struct uart_ns16550_dev_data * const dev_data = dev->data;
988 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
989
990 dev_data->cb = cb;
991 dev_data->cb_data = cb_data;
992
993 k_spin_unlock(&dev_data->lock, key);
994 }
995
996 /**
997 * @brief Interrupt service routine.
998 *
999 * This simply calls the callback function, if one exists.
1000 *
1001 * @param arg Argument to ISR.
1002 */
1003 static void uart_ns16550_isr(const struct device *dev)
1004 {
1005 struct uart_ns16550_dev_data * const dev_data = dev->data;
1006
1007 if (dev_data->cb) {
1008 dev_data->cb(dev, dev_data->cb_data);
1009 }
1010
1011 #ifdef CONFIG_UART_NS16550_WA_ISR_REENABLE_INTERRUPT
1012 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
1013 uint8_t cached_ier = ns16550_inbyte(dev_cfg, IER(dev));
1014
1015 ns16550_outbyte(dev_cfg, IER(dev), 0U);
1016 ns16550_outbyte(dev_cfg, IER(dev), cached_ier);
1017 #endif
1018 }
1019
1020 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
1021
1022 #ifdef CONFIG_UART_NS16550_LINE_CTRL
1023
1024 /**
1025 * @brief Manipulate line control for UART.
1026 *
1027 * @param dev UART device struct
1028 * @param ctrl The line control to be manipulated
1029 * @param val Value to set the line control
1030 *
1031 * @return 0 if successful, failed otherwise
1032 */
1033 static int uart_ns16550_line_ctrl_set(const struct device *dev,
1034 uint32_t ctrl, uint32_t val)
1035 {
1036 struct uart_ns16550_dev_data *data = dev->data;
1037 const struct uart_ns16550_device_config *const dev_cfg = dev->config;
1038 uint32_t mdc, chg, pclk = 0U;
1039 k_spinlock_key_t key;
1040
1041 if (dev_cfg->sys_clk_freq != 0U) {
1042 pclk = dev_cfg->sys_clk_freq;
1043 } else {
1044 if (device_is_ready(dev_cfg->clock_dev)) {
1045 clock_control_get_rate(dev_cfg->clock_dev, dev_cfg->clock_subsys, &pclk);
1046 }
1047 }
1048
1049 switch (ctrl) {
1050 case UART_LINE_CTRL_BAUD_RATE:
1051 set_baud_rate(dev, val, pclk);
1052 return 0;
1053
1054 case UART_LINE_CTRL_RTS:
1055 case UART_LINE_CTRL_DTR:
1056 key = k_spin_lock(&data->lock);
1057 mdc = ns16550_inbyte(dev_cfg, MDC(dev));
1058
1059 if (ctrl == UART_LINE_CTRL_RTS) {
1060 chg = MCR_RTS;
1061 } else {
1062 chg = MCR_DTR;
1063 }
1064
1065 if (val) {
1066 mdc |= chg;
1067 } else {
1068 mdc &= ~(chg);
1069 }
1070 ns16550_outbyte(dev_cfg, MDC(dev), mdc);
1071 k_spin_unlock(&data->lock, key);
1072 return 0;
1073 }
1074
1075 return -ENOTSUP;
1076 }
1077
1078 #endif /* CONFIG_UART_NS16550_LINE_CTRL */
1079
1080 #ifdef CONFIG_UART_NS16550_DRV_CMD
1081
1082 /**
1083 * @brief Send extra command to driver
1084 *
1085 * @param dev UART device struct
1086 * @param cmd Command to driver
1087 * @param p Parameter to the command
1088 *
1089 * @return 0 if successful, failed otherwise
1090 */
1091 static int uart_ns16550_drv_cmd(const struct device *dev, uint32_t cmd,
1092 uint32_t p)
1093 {
1094 #if UART_NS16550_DLF_ENABLED
1095 if (cmd == CMD_SET_DLF) {
1096 struct uart_ns16550_dev_data * const dev_data = dev->data;
1097 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
1098 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
1099
1100 dev_data->dlf = p;
1101 ns16550_outbyte(dev_cfg, DLF(dev), dev_data->dlf);
1102 k_spin_unlock(&dev_data->lock, key);
1103 return 0;
1104 }
1105 #endif
1106
1107 return -ENOTSUP;
1108 }
1109
1110 #endif /* CONFIG_UART_NS16550_DRV_CMD */
1111
1112
1113 static const struct uart_driver_api uart_ns16550_driver_api = {
1114 .poll_in = uart_ns16550_poll_in,
1115 .poll_out = uart_ns16550_poll_out,
1116 .err_check = uart_ns16550_err_check,
1117 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
1118 .configure = uart_ns16550_configure,
1119 .config_get = uart_ns16550_config_get,
1120 #endif
1121 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1122
1123 .fifo_fill = uart_ns16550_fifo_fill,
1124 .fifo_read = uart_ns16550_fifo_read,
1125 .irq_tx_enable = uart_ns16550_irq_tx_enable,
1126 .irq_tx_disable = uart_ns16550_irq_tx_disable,
1127 .irq_tx_ready = uart_ns16550_irq_tx_ready,
1128 .irq_tx_complete = uart_ns16550_irq_tx_complete,
1129 .irq_rx_enable = uart_ns16550_irq_rx_enable,
1130 .irq_rx_disable = uart_ns16550_irq_rx_disable,
1131 .irq_rx_ready = uart_ns16550_irq_rx_ready,
1132 .irq_err_enable = uart_ns16550_irq_err_enable,
1133 .irq_err_disable = uart_ns16550_irq_err_disable,
1134 .irq_is_pending = uart_ns16550_irq_is_pending,
1135 .irq_update = uart_ns16550_irq_update,
1136 .irq_callback_set = uart_ns16550_irq_callback_set,
1137
1138 #endif
1139
1140 #ifdef CONFIG_UART_NS16550_LINE_CTRL
1141 .line_ctrl_set = uart_ns16550_line_ctrl_set,
1142 #endif
1143
1144 #ifdef CONFIG_UART_NS16550_DRV_CMD
1145 .drv_cmd = uart_ns16550_drv_cmd,
1146 #endif
1147 };
1148
1149 #define UART_NS16550_IRQ_FLAGS_SENSE0(n) 0
1150 #define UART_NS16550_IRQ_FLAGS_SENSE1(n) DT_INST_IRQ(n, sense)
1151 #define UART_NS16550_IRQ_FLAGS(n) \
1152 _CONCAT(UART_NS16550_IRQ_FLAGS_SENSE, DT_INST_IRQ_HAS_CELL(n, sense))(n)
1153
1154 /* not PCI(e) */
1155 #define UART_NS16550_IRQ_CONFIG_PCIE0(n) \
1156 static void irq_config_func##n(const struct device *dev) \
1157 { \
1158 ARG_UNUSED(dev); \
1159 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
1160 uart_ns16550_isr, DEVICE_DT_INST_GET(n), \
1161 UART_NS16550_IRQ_FLAGS(n)); \
1162 irq_enable(DT_INST_IRQN(n)); \
1163 }
1164
1165 /* PCI(e) with auto IRQ detection */
1166 #define UART_NS16550_IRQ_CONFIG_PCIE1(n) \
1167 static void irq_config_func##n(const struct device *dev) \
1168 { \
1169 BUILD_ASSERT(DT_INST_IRQN(n) == PCIE_IRQ_DETECT, \
1170 "Only runtime IRQ configuration is supported"); \
1171 BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS), \
1172 "NS16550 PCIe requires dynamic interrupts"); \
1173 const struct uart_ns16550_device_config *dev_cfg = dev->config;\
1174 unsigned int irq = pcie_alloc_irq(dev_cfg->pcie->bdf); \
1175 if (irq == PCIE_CONF_INTR_IRQ_NONE) { \
1176 return; \
1177 } \
1178 pcie_connect_dynamic_irq(dev_cfg->pcie->bdf, irq, \
1179 DT_INST_IRQ(n, priority), \
1180 (void (*)(const void *))uart_ns16550_isr, \
1181 DEVICE_DT_INST_GET(n), \
1182 UART_NS16550_IRQ_FLAGS(n)); \
1183 pcie_irq_enable(dev_cfg->pcie->bdf, irq); \
1184 }
1185
1186 #ifdef CONFIG_UART_NS16550_ACCESS_IOPORT
1187 #define REG_INIT(n) \
1188 .port = DT_INST_REG_ADDR(n), \
1189 .io_map = true,
1190 #else
1191 #define REG_INIT_PCIE1(n)
1192 #define REG_INIT_PCIE0(n) DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)),
1193
1194 #define DEV_REG_PORT_IO_1(n) \
1195 .port = DT_INST_REG_ADDR(n),
1196 #define DEV_REG_PORT_IO_0(n) \
1197 _CONCAT(REG_INIT_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1198 #ifdef CONFIG_UART_NS16550_SIMULT_ACCESS
1199 #define DEV_IO_INIT(n) \
1200 .io_map = DT_INST_PROP(n, io_mapped),
1201 #else
1202 #define DEV_IO_INIT(n)
1203 #endif
1204
1205 #define REG_INIT(n) \
1206 _CONCAT(DEV_REG_PORT_IO_, DT_INST_PROP(n, io_mapped))(n) \
1207 DEV_IO_INIT(n)
1208 #endif
1209
1210 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1211 #define DEV_CONFIG_IRQ_FUNC_INIT(n) \
1212 .irq_config_func = irq_config_func##n,
1213 #define UART_NS16550_IRQ_FUNC_DECLARE(n) \
1214 static void irq_config_func##n(const struct device *dev);
1215 #define UART_NS16550_IRQ_FUNC_DEFINE(n) \
1216 _CONCAT(UART_NS16550_IRQ_CONFIG_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1217 #else
1218 /* !CONFIG_UART_INTERRUPT_DRIVEN */
1219 #define DEV_CONFIG_IRQ_FUNC_INIT(n)
1220 #define UART_NS16550_IRQ_FUNC_DECLARE(n)
1221 #define UART_NS16550_IRQ_FUNC_DEFINE(n)
1222 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
1223
1224 #if UART_NS16550_PCP_ENABLED
1225 #define DEV_CONFIG_PCP_INIT(n) .pcp = DT_INST_PROP_OR(n, pcp, 0),
1226 #else
1227 #define DEV_CONFIG_PCP_INIT(n)
1228 #endif
1229
1230 #define DEV_CONFIG_PCIE0(n)
1231 #define DEV_CONFIG_PCIE1(n) DEVICE_PCIE_INST_INIT(n, pcie)
1232 #define DEV_CONFIG_PCIE_INIT(n) \
1233 _CONCAT(DEV_CONFIG_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1234
1235 #define DEV_DECLARE_PCIE0(n)
1236 #define DEV_DECLARE_PCIE1(n) DEVICE_PCIE_INST_DECLARE(n)
1237 #define DEV_PCIE_DECLARE(n) \
1238 _CONCAT(DEV_DECLARE_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1239
1240 #define DEV_DATA_FLOW_CTRL0 UART_CFG_FLOW_CTRL_NONE
1241 #define DEV_DATA_FLOW_CTRL1 UART_CFG_FLOW_CTRL_RTS_CTS
1242 #define DEV_DATA_FLOW_CTRL(n) \
1243 _CONCAT(DEV_DATA_FLOW_CTRL, DT_INST_PROP_OR(n, hw_flow_control, 0))
1244
1245 #define DEV_DATA_DLF0(n)
1246 #define DEV_DATA_DLF1(n) \
1247 .dlf = DT_INST_PROP(n, dlf),
1248 #define DEV_DATA_DLF_INIT(n) \
1249 _CONCAT(DEV_DATA_DLF, DT_INST_NODE_HAS_PROP(n, dlf))(n)
1250
1251 #define UART_NS16550_DEVICE_INIT(n) \
1252 UART_NS16550_IRQ_FUNC_DECLARE(n); \
1253 DEV_PCIE_DECLARE(n); \
1254 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pinctrl_0), \
1255 (PINCTRL_DT_INST_DEFINE(n))); \
1256 static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_##n = { \
1257 REG_INIT(n) \
1258 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, clock_frequency), ( \
1259 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
1260 .clock_dev = NULL, \
1261 .clock_subsys = NULL, \
1262 ), ( \
1263 .sys_clk_freq = 0, \
1264 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
1265 .clock_subsys = (clock_control_subsys_t) DT_INST_PHA(\
1266 0, clocks, clkid), \
1267 ) \
1268 ) \
1269 DEV_CONFIG_IRQ_FUNC_INIT(n) \
1270 DEV_CONFIG_PCP_INIT(n) \
1271 .reg_interval = (1 << DT_INST_PROP(n, reg_shift)), \
1272 DEV_CONFIG_PCIE_INIT(n) \
1273 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pinctrl_0), \
1274 (.pincfg = PINCTRL_DT_DEV_CONFIG_GET(DT_DRV_INST(n)),)) \
1275 }; \
1276 static struct uart_ns16550_dev_data uart_ns16550_dev_data_##n = { \
1277 .uart_config.baudrate = DT_INST_PROP_OR(n, current_speed, 0), \
1278 .uart_config.parity = UART_CFG_PARITY_NONE, \
1279 .uart_config.stop_bits = UART_CFG_STOP_BITS_1, \
1280 .uart_config.data_bits = UART_CFG_DATA_BITS_8, \
1281 .uart_config.flow_ctrl = DEV_DATA_FLOW_CTRL(n), \
1282 DEV_DATA_DLF_INIT(n) \
1283 }; \
1284 DEVICE_DT_INST_DEFINE(n, &uart_ns16550_init, NULL, \
1285 &uart_ns16550_dev_data_##n, &uart_ns16550_dev_cfg_##n, \
1286 PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
1287 &uart_ns16550_driver_api); \
1288 UART_NS16550_IRQ_FUNC_DEFINE(n)
1289
1290 DT_INST_FOREACH_STATUS_OKAY(UART_NS16550_DEVICE_INIT)
1291
