1 /*
2 * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT neorv32_uart
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/syscon.h>
11 #include <zephyr/drivers/uart.h>
12 #include <zephyr/pm/device.h>
13 #include <zephyr/sys/sys_io.h>
14
15 #include <zephyr/logging/log.h>
16 #include <zephyr/irq.h>
17 LOG_MODULE_REGISTER(uart_neorv32, CONFIG_UART_LOG_LEVEL);
18
19 /* NEORV32 UART registers offsets */
20 #define NEORV32_UART_CTRL_OFFSET 0x00
21 #define NEORV32_UART_DATA_OFFSET 0x04
22
23 /* UART_CTRL register bits */
24 #define NEORV32_UART_CTRL_BAUD_MASK BIT_MASK(12)
25 #define NEORV32_UART_CTRL_BAUD_POS 0U
26 #define NEORV32_UART_CTRL_PRSC_MASK BIT_MASK(3)
27 #define NEORV32_UART_CTRL_PRSC_POS 24U
28 #define NEORV32_UART_CTRL_RTS_EN BIT(20)
29 #define NEORV32_UART_CTRL_CTS_EN BIT(21)
30 #define NEORV32_UART_CTRL_PMODE_NONE BIT(22)
31 #define NEORV32_UART_CTRL_PMODE_EVEN BIT(23)
32 #define NEORV32_UART_CTRL_PMODE_ODD (BIT(22) | BIT(23))
33 #define NEORV32_UART_CTRL_EN BIT(28)
34 #define NEORV32_UART_CTRL_TX_BUSY BIT(31)
35
36 /* UART_DATA register status bits */
37 #define NEORV32_UART_DATA_PERR BIT(28)
38 #define NEORV32_UART_DATA_FERR BIT(29)
39 #define NEORV32_UART_DATA_OVERR BIT(30)
40 #define NEORV32_UART_DATA_AVAIL BIT(31)
41
42 struct neorv32_uart_config {
43 const struct device *syscon;
44 uint32_t feature_mask;
45 mm_reg_t base;
46 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
47 void (*irq_config_func)(const struct device *dev);
48 unsigned int tx_irq;
49 unsigned int rx_irq;
50 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
51 };
52
53 struct neorv32_uart_data {
54 struct uart_config uart_cfg;
55 uint32_t last_data;
56 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
57 struct k_timer timer;
58 uart_irq_callback_user_data_t callback;
59 void *callback_data;
60 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
61 };
62
neorv32_uart_read_ctrl(const struct device * dev)63 static inline uint32_t neorv32_uart_read_ctrl(const struct device *dev)
64 {
65 const struct neorv32_uart_config *config = dev->config;
66
67 return sys_read32(config->base + NEORV32_UART_CTRL_OFFSET);
68 }
69
neorv32_uart_write_ctrl(const struct device * dev,uint32_t ctrl)70 static inline void neorv32_uart_write_ctrl(const struct device *dev, uint32_t ctrl)
71 {
72 const struct neorv32_uart_config *config = dev->config;
73
74 sys_write32(ctrl, config->base + NEORV32_UART_CTRL_OFFSET);
75 }
76
neorv32_uart_read_data(const struct device * dev)77 static inline uint32_t neorv32_uart_read_data(const struct device *dev)
78 {
79 const struct neorv32_uart_config *config = dev->config;
80 struct neorv32_uart_data *data = dev->data;
81 uint32_t reg;
82
83 /* Cache status bits as they are cleared upon read */
84 reg = sys_read32(config->base + NEORV32_UART_DATA_OFFSET);
85 data->last_data = reg;
86
87 return reg;
88 }
89
neorv32_uart_write_data(const struct device * dev,uint32_t data)90 static inline void neorv32_uart_write_data(const struct device *dev, uint32_t data)
91 {
92 const struct neorv32_uart_config *config = dev->config;
93
94 sys_write32(data, config->base + NEORV32_UART_DATA_OFFSET);
95 }
96
neorv32_uart_poll_in(const struct device * dev,unsigned char * c)97 static int neorv32_uart_poll_in(const struct device *dev, unsigned char *c)
98 {
99 uint32_t data;
100
101 data = neorv32_uart_read_data(dev);
102
103 if ((data & NEORV32_UART_DATA_AVAIL) != 0) {
104 *c = data & BIT_MASK(8);
105 return 0;
106 }
107
108 return -1;
109 }
110
neorv32_uart_poll_out(const struct device * dev,unsigned char c)111 static void neorv32_uart_poll_out(const struct device *dev, unsigned char c)
112 {
113 while ((neorv32_uart_read_ctrl(dev) & NEORV32_UART_CTRL_TX_BUSY) != 0) {
114 }
115
116 neorv32_uart_write_data(dev, c);
117 }
118
neorv32_uart_err_check(const struct device * dev)119 static int neorv32_uart_err_check(const struct device *dev)
120 {
121 struct neorv32_uart_data *data = dev->data;
122 int err = 0;
123
124 if ((data->last_data & NEORV32_UART_DATA_OVERR) != 0) {
125 err |= UART_ERROR_OVERRUN;
126 }
127
128 if ((data->last_data & NEORV32_UART_DATA_PERR) != 0) {
129 err |= UART_ERROR_PARITY;
130 }
131
132 if ((data->last_data & NEORV32_UART_DATA_FERR) != 0) {
133 err |= UART_ERROR_FRAMING;
134 }
135
136 data->last_data &= ~(NEORV32_UART_DATA_OVERR | NEORV32_UART_DATA_PERR |
137 NEORV32_UART_DATA_FERR);
138
139 return err;
140 }
141
neorv32_uart_configure(const struct device * dev,const struct uart_config * cfg)142 static int neorv32_uart_configure(const struct device *dev, const struct uart_config *cfg)
143 {
144 const struct neorv32_uart_config *config = dev->config;
145 struct neorv32_uart_data *data = dev->data;
146 uint32_t ctrl = NEORV32_UART_CTRL_EN;
147 uint16_t baudxx = 0;
148 uint8_t prscx = 0;
149 uint32_t clk;
150 int err;
151
152 __ASSERT_NO_MSG(cfg != NULL);
153
154 if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
155 LOG_ERR("hardware only supports one stop bit");
156 return -ENOTSUP;
157 }
158
159 if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
160 LOG_ERR("hardware only supports 8 data bits");
161 return -ENOTSUP;
162 }
163
164 switch (cfg->parity) {
165 case UART_CFG_PARITY_NONE:
166 ctrl |= NEORV32_UART_CTRL_PMODE_NONE;
167 break;
168 case UART_CFG_PARITY_ODD:
169 ctrl |= NEORV32_UART_CTRL_PMODE_ODD;
170 break;
171 case UART_CFG_PARITY_EVEN:
172 ctrl |= NEORV32_UART_CTRL_PMODE_EVEN;
173 break;
174 default:
175 LOG_ERR("unsupported parity mode %d", cfg->parity);
176 return -ENOTSUP;
177 }
178
179 switch (cfg->flow_ctrl) {
180 case UART_CFG_FLOW_CTRL_NONE:
181 ctrl |= 0;
182 break;
183 case UART_CFG_FLOW_CTRL_RTS_CTS:
184 ctrl |= NEORV32_UART_CTRL_RTS_EN | NEORV32_UART_CTRL_CTS_EN;
185 break;
186 default:
187 LOG_ERR("unsupported flow control mode %d", cfg->flow_ctrl);
188 return -ENOTSUP;
189 }
190
191 err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_CLK, &clk);
192 if (err < 0) {
193 LOG_ERR("failed to determine clock rate (err %d)", err);
194 return -EIO;
195 }
196
197 if (cfg->baudrate == 0) {
198 LOG_ERR("invalid baud rate 0");
199 return -EINVAL;
200 }
201
202 /*
203 * Calculate clock prescaler and baud prescaler. Initial prscx = 0 is
204 * clock / 2.
205 */
206 baudxx = clk / (2 * cfg->baudrate);
207 while (baudxx >= NEORV32_UART_CTRL_BAUD_MASK) {
208 if ((prscx == 2) || (prscx == 4)) {
209 baudxx >>= 3;
210 } else {
211 baudxx >>= 1;
212 }
213
214 prscx++;
215 }
216
217 if (prscx > NEORV32_UART_CTRL_PRSC_MASK) {
218 LOG_ERR("unsupported baud rate %d", cfg->baudrate);
219 return -ENOTSUP;
220 }
221
222 ctrl |= (baudxx - 1) << NEORV32_UART_CTRL_BAUD_POS;
223 ctrl |= prscx << NEORV32_UART_CTRL_PRSC_POS;
224
225 data->uart_cfg = *cfg;
226 neorv32_uart_write_ctrl(dev, ctrl);
227
228 return 0;
229 }
230
neorv32_uart_config_get(const struct device * dev,struct uart_config * cfg)231 static int neorv32_uart_config_get(const struct device *dev, struct uart_config *cfg)
232 {
233 struct neorv32_uart_data *data = dev->data;
234
235 __ASSERT_NO_MSG(cfg != NULL);
236
237 *cfg = data->uart_cfg;
238
239 return 0;
240 }
241
242 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
neorv32_uart_fifo_fill(const struct device * dev,const uint8_t * tx_data,int len)243 static int neorv32_uart_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
244 {
245 uint32_t ctrl;
246
247 if (len <= 0) {
248 return 0;
249 }
250
251 __ASSERT_NO_MSG(tx_data != NULL);
252
253 ctrl = neorv32_uart_read_ctrl(dev);
254 if ((ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0) {
255 neorv32_uart_write_data(dev, *tx_data);
256 return 1;
257 }
258
259 return 0;
260 }
261
neorv32_uart_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)262 static int neorv32_uart_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
263 {
264 struct neorv32_uart_data *data = dev->data;
265 int count = 0;
266
267 if (size <= 0) {
268 return 0;
269 }
270
271 __ASSERT_NO_MSG(rx_data != NULL);
272
273 while ((data->last_data & NEORV32_UART_DATA_AVAIL) != 0) {
274 rx_data[count++] = data->last_data & BIT_MASK(8);
275 data->last_data &= ~(NEORV32_UART_DATA_AVAIL);
276
277 if (count >= size) {
278 break;
279 }
280
281 (void)neorv32_uart_read_data(dev);
282 }
283
284 return count;
285 }
286
neorv32_uart_tx_soft_isr(struct k_timer * timer)287 static void neorv32_uart_tx_soft_isr(struct k_timer *timer)
288 {
289 const struct device *dev = k_timer_user_data_get(timer);
290 struct neorv32_uart_data *data = dev->data;
291 uart_irq_callback_user_data_t callback = data->callback;
292
293 if (callback) {
294 callback(dev, data->callback_data);
295 }
296 }
297
neorv32_uart_irq_tx_enable(const struct device * dev)298 static void neorv32_uart_irq_tx_enable(const struct device *dev)
299 {
300 const struct neorv32_uart_config *config = dev->config;
301 struct neorv32_uart_data *data = dev->data;
302 uint32_t ctrl;
303
304 irq_enable(config->tx_irq);
305
306 ctrl = neorv32_uart_read_ctrl(dev);
307 if ((ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0) {
308 /*
309 * TX done event already generated an edge interrupt. Generate a
310 * soft interrupt and have it call the callback function in
311 * timer isr context.
312 */
313 k_timer_start(&data->timer, K_NO_WAIT, K_NO_WAIT);
314 }
315 }
316
neorv32_uart_irq_tx_disable(const struct device * dev)317 static void neorv32_uart_irq_tx_disable(const struct device *dev)
318 {
319 const struct neorv32_uart_config *config = dev->config;
320
321 irq_disable(config->tx_irq);
322 }
323
neorv32_uart_irq_tx_ready(const struct device * dev)324 static int neorv32_uart_irq_tx_ready(const struct device *dev)
325 {
326 const struct neorv32_uart_config *config = dev->config;
327 uint32_t ctrl;
328
329 if (!irq_is_enabled(config->tx_irq)) {
330 return 0;
331 }
332
333 ctrl = neorv32_uart_read_ctrl(dev);
334
335 return (ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0;
336 }
337
neorv32_uart_irq_rx_enable(const struct device * dev)338 static void neorv32_uart_irq_rx_enable(const struct device *dev)
339 {
340 const struct neorv32_uart_config *config = dev->config;
341
342 irq_enable(config->rx_irq);
343 }
344
neorv32_uart_irq_rx_disable(const struct device * dev)345 static void neorv32_uart_irq_rx_disable(const struct device *dev)
346 {
347 const struct neorv32_uart_config *config = dev->config;
348
349 irq_disable(config->rx_irq);
350 }
351
neorv32_uart_irq_tx_complete(const struct device * dev)352 static int neorv32_uart_irq_tx_complete(const struct device *dev)
353 {
354 uint32_t ctrl;
355
356 ctrl = neorv32_uart_read_ctrl(dev);
357
358 return (ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0;
359 }
360
neorv32_uart_irq_rx_ready(const struct device * dev)361 static int neorv32_uart_irq_rx_ready(const struct device *dev)
362 {
363 const struct neorv32_uart_config *config = dev->config;
364 struct neorv32_uart_data *data = dev->data;
365
366 if (!irq_is_enabled(config->rx_irq)) {
367 return 0;
368 }
369
370 return (data->last_data & NEORV32_UART_DATA_AVAIL) != 0;
371 }
372
neorv32_uart_irq_is_pending(const struct device * dev)373 static int neorv32_uart_irq_is_pending(const struct device *dev)
374 {
375 return (neorv32_uart_irq_tx_ready(dev) ||
376 neorv32_uart_irq_rx_ready(dev));
377 }
378
neorv32_uart_irq_update(const struct device * dev)379 static int neorv32_uart_irq_update(const struct device *dev)
380 {
381 const struct neorv32_uart_config *config = dev->config;
382
383 if (irq_is_enabled(config->rx_irq)) {
384 /* Cache data for use by rx_ready() and fifo_read() */
385 (void)neorv32_uart_read_data(dev);
386 }
387
388 return 1;
389 }
390
neorv32_uart_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * user_data)391 static void neorv32_uart_irq_callback_set(const struct device *dev,
392 uart_irq_callback_user_data_t cb, void *user_data)
393 {
394 struct neorv32_uart_data *data = dev->data;
395
396 data->callback = cb;
397 data->callback_data = user_data;
398 }
399
neorv32_uart_isr(const struct device * dev)400 static void neorv32_uart_isr(const struct device *dev)
401 {
402 struct neorv32_uart_data *data = dev->data;
403 uart_irq_callback_user_data_t callback = data->callback;
404
405 if (callback) {
406 callback(dev, data->callback_data);
407 }
408 }
409 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
410
neorv32_uart_init(const struct device * dev)411 static int neorv32_uart_init(const struct device *dev)
412 {
413 const struct neorv32_uart_config *config = dev->config;
414 struct neorv32_uart_data *data = dev->data;
415 uint32_t features;
416 int err;
417
418 if (!device_is_ready(config->syscon)) {
419 LOG_ERR("syscon device not ready");
420 return -EINVAL;
421 }
422
423 err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_FEATURES, &features);
424 if (err < 0) {
425 LOG_ERR("failed to determine implemented features (err %d)", err);
426 return -EIO;
427 }
428
429 if ((features & config->feature_mask) == 0) {
430 LOG_ERR("neorv32 uart instance not supported");
431 return -ENODEV;
432 }
433
434 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
435 k_timer_init(&data->timer, &neorv32_uart_tx_soft_isr, NULL);
436 k_timer_user_data_set(&data->timer, (void *)dev);
437
438 config->irq_config_func(dev);
439 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
440
441 return neorv32_uart_configure(dev, &data->uart_cfg);
442 }
443
444 #ifdef CONFIG_PM_DEVICE
neorv32_uart_pm_action(const struct device * dev,enum pm_device_action action)445 static int neorv32_uart_pm_action(const struct device *dev,
446 enum pm_device_action action)
447 {
448 uint32_t ctrl = neorv32_uart_read_ctrl(dev);
449
450 switch (action) {
451 case PM_DEVICE_ACTION_SUSPEND:
452 ctrl &= ~(NEORV32_UART_CTRL_EN);
453 break;
454 case PM_DEVICE_ACTION_RESUME:
455 ctrl |= NEORV32_UART_CTRL_EN;
456 break;
457 default:
458 return -ENOTSUP;
459 }
460
461 neorv32_uart_write_ctrl(dev, ctrl);
462
463 return 0;
464 }
465 #endif /* CONFIG_PM_DEVICE */
466
467 static const struct uart_driver_api neorv32_uart_driver_api = {
468 .poll_in = neorv32_uart_poll_in,
469 .poll_out = neorv32_uart_poll_out,
470 .err_check = neorv32_uart_err_check,
471 .configure = neorv32_uart_configure,
472 .config_get = neorv32_uart_config_get,
473 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
474 .fifo_fill = neorv32_uart_fifo_fill,
475 .fifo_read = neorv32_uart_fifo_read,
476 .irq_tx_enable = neorv32_uart_irq_tx_enable,
477 .irq_tx_disable = neorv32_uart_irq_tx_disable,
478 .irq_tx_ready = neorv32_uart_irq_tx_ready,
479 .irq_rx_enable = neorv32_uart_irq_rx_enable,
480 .irq_rx_disable = neorv32_uart_irq_rx_disable,
481 .irq_tx_complete = neorv32_uart_irq_tx_complete,
482 .irq_rx_ready = neorv32_uart_irq_rx_ready,
483 .irq_is_pending = neorv32_uart_irq_is_pending,
484 .irq_update = neorv32_uart_irq_update,
485 .irq_callback_set = neorv32_uart_irq_callback_set,
486 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
487 };
488
489 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
490 #define NEORV32_UART_CONFIG_FUNC(node_id, n) \
491 static void neorv32_uart_config_func_##n(const struct device *dev) \
492 { \
493 IRQ_CONNECT(DT_IRQ_BY_NAME(node_id, tx, irq), \
494 DT_IRQ_BY_NAME(node_id, tx, priority), \
495 neorv32_uart_isr, \
496 DEVICE_DT_GET(node_id), 0); \
497 \
498 IRQ_CONNECT(DT_IRQ_BY_NAME(node_id, rx, irq), \
499 DT_IRQ_BY_NAME(node_id, rx, priority), \
500 neorv32_uart_isr, \
501 DEVICE_DT_GET(node_id), 0); \
502 }
503 #define NEORV32_UART_CONFIG_INIT(node_id, n) \
504 .irq_config_func = neorv32_uart_config_func_##n, \
505 .tx_irq = DT_IRQ_BY_NAME(node_id, tx, irq), \
506 .rx_irq = DT_IRQ_BY_NAME(node_id, rx, irq),
507 #else
508 #define NEORV32_UART_CONFIG_FUNC(node_id, n)
509 #define NEORV32_UART_CONFIG_INIT(node_id, n)
510 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
511
512 #define NEORV32_UART_INIT(node_id, n) \
513 NEORV32_UART_CONFIG_FUNC(node_id, n) \
514 \
515 static struct neorv32_uart_data neorv32_uart_##n##_data = { \
516 .uart_cfg = { \
517 .baudrate = DT_PROP(node_id, current_speed), \
518 .parity = DT_ENUM_IDX_OR(node_id, parity, \
519 UART_CFG_PARITY_NONE), \
520 .stop_bits = UART_CFG_STOP_BITS_1, \
521 .data_bits = UART_CFG_DATA_BITS_8, \
522 .flow_ctrl = DT_PROP(node_id, hw_flow_control) ? \
523 UART_CFG_FLOW_CTRL_RTS_CTS : \
524 UART_CFG_FLOW_CTRL_NONE, \
525 }, \
526 }; \
527 \
528 static const struct neorv32_uart_config neorv32_uart_##n##_config = { \
529 .syscon = DEVICE_DT_GET(DT_PHANDLE(node_id, syscon)), \
530 .feature_mask = NEORV32_SYSINFO_FEATURES_IO_UART##n, \
531 .base = DT_REG_ADDR(node_id), \
532 NEORV32_UART_CONFIG_INIT(node_id, n) \
533 }; \
534 \
535 PM_DEVICE_DT_DEFINE(node_id, neorv32_uart_pm_action); \
536 \
537 DEVICE_DT_DEFINE(node_id, &neorv32_uart_init, \
538 PM_DEVICE_DT_GET(node_id), \
539 &neorv32_uart_##n##_data, \
540 &neorv32_uart_##n##_config, \
541 PRE_KERNEL_1, \
542 CONFIG_SERIAL_INIT_PRIORITY, \
543 &neorv32_uart_driver_api)
544
545 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(uart0), DT_DRV_COMPAT, okay)
546 NEORV32_UART_INIT(DT_NODELABEL(uart0), 0);
547 #endif
548
549 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(uart1), DT_DRV_COMPAT, okay)
550 NEORV32_UART_INIT(DT_NODELABEL(uart1), 1);
551 #endif
552
