1 /*
2 * Copyright 2019 Henrik Brix Andersen <henrik@brixandersen.dk>
3 *
4 * Heavily based on pwm_mcux_ftm.c, which is:
5 * Copyright (c) 2017, NXP
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9
10 #define DT_DRV_COMPAT openisa_rv32m1_tpm
11
12 #include <zephyr/drivers/clock_control.h>
13 #include <errno.h>
14 #include <zephyr/drivers/pwm.h>
15 #include <soc.h>
16 #include <fsl_tpm.h>
17 #include <fsl_clock.h>
18 #include <zephyr/drivers/pinctrl.h>
19
20 #include <zephyr/logging/log.h>
21
22 LOG_MODULE_REGISTER(pwm_rv32m1_tpm, CONFIG_PWM_LOG_LEVEL);
23
24 #define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)
25
26 struct rv32m1_tpm_config {
27 TPM_Type *base;
28 const struct device *clock_dev;
29 clock_control_subsys_t clock_subsys;
30 tpm_clock_source_t tpm_clock_source;
31 tpm_clock_prescale_t prescale;
32 uint8_t channel_count;
33 tpm_pwm_mode_t mode;
34 const struct pinctrl_dev_config *pincfg;
35 };
36
37 struct rv32m1_tpm_data {
38 uint32_t clock_freq;
39 uint32_t period_cycles;
40 tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS];
41 };
42
rv32m1_tpm_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)43 static int rv32m1_tpm_set_cycles(const struct device *dev, uint32_t channel,
44 uint32_t period_cycles, uint32_t pulse_cycles,
45 pwm_flags_t flags)
46 {
47 const struct rv32m1_tpm_config *config = dev->config;
48 struct rv32m1_tpm_data *data = dev->data;
49 uint8_t duty_cycle;
50
51 if (period_cycles == 0U) {
52 LOG_ERR("Channel can not be set to inactive level");
53 return -ENOTSUP;
54 }
55
56 if (channel >= config->channel_count) {
57 LOG_ERR("Invalid channel");
58 return -ENOTSUP;
59 }
60
61 duty_cycle = pulse_cycles * 100U / period_cycles;
62 data->channel[channel].dutyCyclePercent = duty_cycle;
63
64 if ((flags & PWM_POLARITY_INVERTED) == 0) {
65 data->channel[channel].level = kTPM_HighTrue;
66 } else {
67 data->channel[channel].level = kTPM_LowTrue;
68 }
69
70 LOG_DBG("pulse_cycles=%d, period_cycles=%d, duty_cycle=%d, flags=%d",
71 pulse_cycles, period_cycles, duty_cycle, flags);
72
73 if (period_cycles != data->period_cycles) {
74 uint32_t pwm_freq;
75 status_t status;
76
77 if (data->period_cycles != 0) {
78 /* Only warn when not changing from zero */
79 LOG_WRN("Changing period cycles from %d to %d"
80 " affects all %d channels in %s",
81 data->period_cycles, period_cycles,
82 config->channel_count, dev->name);
83 }
84
85 data->period_cycles = period_cycles;
86
87 pwm_freq = (data->clock_freq >> config->prescale) /
88 period_cycles;
89
90 LOG_DBG("pwm_freq=%d, clock_freq=%d", pwm_freq,
91 data->clock_freq);
92
93 if (pwm_freq == 0U) {
94 LOG_ERR("Could not set up pwm_freq=%d", pwm_freq);
95 return -EINVAL;
96 }
97
98 TPM_StopTimer(config->base);
99
100 status = TPM_SetupPwm(config->base, data->channel,
101 config->channel_count, config->mode,
102 pwm_freq, data->clock_freq);
103
104 if (status != kStatus_Success) {
105 LOG_ERR("Could not set up pwm");
106 return -ENOTSUP;
107 }
108 TPM_StartTimer(config->base, config->tpm_clock_source);
109 } else {
110 TPM_UpdateChnlEdgeLevelSelect(config->base, channel,
111 data->channel[channel].level);
112 TPM_UpdatePwmDutycycle(config->base, channel, config->mode,
113 duty_cycle);
114 }
115
116 return 0;
117 }
118
rv32m1_tpm_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)119 static int rv32m1_tpm_get_cycles_per_sec(const struct device *dev,
120 uint32_t channel, uint64_t *cycles)
121 {
122 const struct rv32m1_tpm_config *config = dev->config;
123 struct rv32m1_tpm_data *data = dev->data;
124
125 *cycles = data->clock_freq >> config->prescale;
126
127 return 0;
128 }
129
rv32m1_tpm_init(const struct device * dev)130 static int rv32m1_tpm_init(const struct device *dev)
131 {
132 const struct rv32m1_tpm_config *config = dev->config;
133 struct rv32m1_tpm_data *data = dev->data;
134 tpm_chnl_pwm_signal_param_t *channel = data->channel;
135 tpm_config_t tpm_config;
136 int err;
137 int i;
138
139 if (config->channel_count > ARRAY_SIZE(data->channel)) {
140 LOG_ERR("Invalid channel count");
141 return -EINVAL;
142 }
143
144 if (!device_is_ready(config->clock_dev)) {
145 LOG_ERR("clock control device not ready");
146 return -ENODEV;
147 }
148
149 if (clock_control_on(config->clock_dev, config->clock_subsys)) {
150 LOG_ERR("Could not turn on clock");
151 return -EINVAL;
152 }
153
154 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
155 &data->clock_freq)) {
156 LOG_ERR("Could not get clock frequency");
157 return -EINVAL;
158 }
159
160 for (i = 0; i < config->channel_count; i++) {
161 channel->chnlNumber = i;
162 channel->level = kTPM_NoPwmSignal;
163 channel->dutyCyclePercent = 0;
164 channel->firstEdgeDelayPercent = 0;
165 channel++;
166 }
167
168 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
169 if (err) {
170 return err;
171 }
172
173 TPM_GetDefaultConfig(&tpm_config);
174 tpm_config.prescale = config->prescale;
175
176 TPM_Init(config->base, &tpm_config);
177
178 return 0;
179 }
180
181 static const struct pwm_driver_api rv32m1_tpm_driver_api = {
182 .set_cycles = rv32m1_tpm_set_cycles,
183 .get_cycles_per_sec = rv32m1_tpm_get_cycles_per_sec,
184 };
185
186 #define TPM_DEVICE(n) \
187 PINCTRL_DT_INST_DEFINE(n); \
188 static const struct rv32m1_tpm_config rv32m1_tpm_config_##n = { \
189 .base = (TPM_Type *) \
190 DT_INST_REG_ADDR(n), \
191 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
192 .clock_subsys = (clock_control_subsys_t) \
193 DT_INST_CLOCKS_CELL(n, name), \
194 .tpm_clock_source = kTPM_SystemClock, \
195 .prescale = kTPM_Prescale_Divide_16, \
196 .channel_count = FSL_FEATURE_TPM_CHANNEL_COUNTn((TPM_Type *) \
197 DT_INST_REG_ADDR(n)), \
198 .mode = kTPM_EdgeAlignedPwm, \
199 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
200 }; \
201 static struct rv32m1_tpm_data rv32m1_tpm_data_##n; \
202 DEVICE_DT_INST_DEFINE(n, &rv32m1_tpm_init, NULL, \
203 &rv32m1_tpm_data_##n, \
204 &rv32m1_tpm_config_##n, \
205 POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
206 &rv32m1_tpm_driver_api);
207
208 DT_INST_FOREACH_STATUS_OKAY(TPM_DEVICE)
209
