1 /*
2 * Copyright (c) 2018 - 2021 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT litex_eth0
8
9 #include <zephyr/kernel.h>
10 #include <zephyr/arch/cpu.h>
11 #include <zephyr/init.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/device.h>
14 #include <zephyr/types.h>
15
16 #define IRQ_MASK DT_REG_ADDR_BY_NAME(DT_INST(0, vexriscv_intc0), irq_mask)
17 #define IRQ_PENDING DT_REG_ADDR_BY_NAME(DT_INST(0, vexriscv_intc0), irq_pending)
18
19 #define TIMER0_IRQ DT_IRQN(DT_INST(0, litex_timer0))
20 #define UART0_IRQ DT_IRQN(DT_INST(0, litex_uart0))
21
22 #define ETH0_IRQ DT_IRQN(DT_INST(0, litex_eth0))
23
24 #define I2S_RX_IRQ DT_IRQN(DT_NODELABEL(i2s_rx))
25 #define I2S_TX_IRQ DT_IRQN(DT_NODELABEL(i2s_tx))
26
27 #define GPIO_IRQ DT_IRQN(DT_NODELABEL(gpio_in))
28
vexriscv_litex_irq_setmask(uint32_t mask)29 static inline void vexriscv_litex_irq_setmask(uint32_t mask)
30 {
31 __asm__ volatile ("csrw %0, %1" :: "i"(IRQ_MASK), "r"(mask));
32 }
33
vexriscv_litex_irq_getmask(void)34 static inline uint32_t vexriscv_litex_irq_getmask(void)
35 {
36 uint32_t mask;
37
38 __asm__ volatile ("csrr %0, %1" : "=r"(mask) : "i"(IRQ_MASK));
39 return mask;
40 }
41
vexriscv_litex_irq_pending(void)42 static inline uint32_t vexriscv_litex_irq_pending(void)
43 {
44 uint32_t pending;
45
46 __asm__ volatile ("csrr %0, %1" : "=r"(pending) : "i"(IRQ_PENDING));
47 return pending;
48 }
49
vexriscv_litex_irq_setie(uint32_t ie)50 static inline void vexriscv_litex_irq_setie(uint32_t ie)
51 {
52 if (ie) {
53 __asm__ volatile ("csrrs x0, mstatus, %0"
54 :: "r"(MSTATUS_IEN));
55 } else {
56 __asm__ volatile ("csrrc x0, mstatus, %0"
57 :: "r"(MSTATUS_IEN));
58 }
59 }
60
vexriscv_litex_irq_handler(const void * device)61 static void vexriscv_litex_irq_handler(const void *device)
62 {
63 struct _isr_table_entry *ite;
64 uint32_t pending, mask, irqs;
65
66 pending = vexriscv_litex_irq_pending();
67 mask = vexriscv_litex_irq_getmask();
68 irqs = pending & mask;
69
70 #ifdef CONFIG_LITEX_TIMER
71 if (irqs & (1 << TIMER0_IRQ)) {
72 ite = &_sw_isr_table[TIMER0_IRQ];
73 ite->isr(ite->arg);
74 }
75 #endif
76
77 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
78 if (irqs & (1 << UART0_IRQ)) {
79 ite = &_sw_isr_table[UART0_IRQ];
80 ite->isr(ite->arg);
81 }
82 #endif
83
84 #ifdef CONFIG_ETH_LITEETH
85 if (irqs & (1 << ETH0_IRQ)) {
86 ite = &_sw_isr_table[ETH0_IRQ];
87 ite->isr(ite->arg);
88 }
89 #endif
90
91 #ifdef CONFIG_I2S
92 if (irqs & (1 << I2S_RX_IRQ)) {
93 ite = &_sw_isr_table[I2S_RX_IRQ];
94 ite->isr(ite->arg);
95 }
96 if (irqs & (1 << I2S_TX_IRQ)) {
97 ite = &_sw_isr_table[I2S_TX_IRQ];
98 ite->isr(ite->arg);
99 }
100 #endif
101
102 if (irqs & (1 << GPIO_IRQ)) {
103 ite = &_sw_isr_table[GPIO_IRQ];
104 ite->isr(ite->arg);
105 }
106 }
107
arch_irq_enable(unsigned int irq)108 void arch_irq_enable(unsigned int irq)
109 {
110 vexriscv_litex_irq_setmask(vexriscv_litex_irq_getmask() | (1 << irq));
111 }
112
arch_irq_disable(unsigned int irq)113 void arch_irq_disable(unsigned int irq)
114 {
115 vexriscv_litex_irq_setmask(vexriscv_litex_irq_getmask() & ~(1 << irq));
116 }
117
arch_irq_is_enabled(unsigned int irq)118 int arch_irq_is_enabled(unsigned int irq)
119 {
120 return vexriscv_litex_irq_getmask() & (1 << irq);
121 }
122
vexriscv_litex_irq_init(void)123 static int vexriscv_litex_irq_init(void)
124 {
125 __asm__ volatile ("csrrs x0, mie, %0"
126 :: "r"(1 << RISCV_MACHINE_EXT_IRQ));
127 vexriscv_litex_irq_setie(1);
128 IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ, 0, vexriscv_litex_irq_handler,
129 NULL, 0);
130
131 return 0;
132 }
133
134 SYS_INIT(vexriscv_litex_irq_init, PRE_KERNEL_2,
135 CONFIG_INTC_INIT_PRIORITY);
136
