1 /* 2 * Copyright (c) 2017 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_DW_H_ 8 #define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_DW_H_ 9 10 #include <zephyr/types.h> 11 12 #ifdef __cplusplus 13 extern "C" { 14 #endif 15 16 typedef void (*dw_ictl_config_irq_t)(const struct device *dev); 17 18 struct dw_ictl_config { 19 uint32_t base_addr; 20 uint32_t numirqs; 21 uint32_t isr_table_offset; 22 dw_ictl_config_irq_t config_func; 23 }; 24 25 struct dw_ictl_registers { 26 uint32_t irq_inten_l; /* offset 00 */ 27 uint32_t irq_inten_h; /* offset 04 */ 28 uint32_t irq_intmask_l; /* offset 08 */ 29 uint32_t irq_intmask_h; /* offset 0C */ 30 uint32_t irq_intforce_l; /* offset 10 */ 31 uint32_t irq_intforce_h; /* offset 14 */ 32 uint32_t irq_rawstatus_l; /* offset 18 */ 33 uint32_t irq_rawstatus_h; /* offset 1c */ 34 uint32_t irq_status_l; /* offset 20 */ 35 uint32_t irq_status_h; /* offset 24 */ 36 uint32_t irq_maskstatus_l; /* offset 28 */ 37 uint32_t irq_maskstatus_h; /* offset 2c */ 38 uint32_t irq_finalstatus_l; /* offset 30 */ 39 uint32_t irq_finalstatus_h; /* offset 34 */ 40 uint32_t irq_vector; /* offset 38 */ 41 uint32_t Reserved1; /* offset 3c */ 42 uint32_t irq_vector_0; /* offset 40 */ 43 uint32_t Reserved2; /* offset 44 */ 44 uint32_t irq_vector_1; /* offset 48 */ 45 uint32_t Reserved3; /* offset 4c */ 46 uint32_t irq_vector_2; /* offset 50 */ 47 uint32_t Reserved4; /* offset 54 */ 48 uint32_t irq_vector_3; /* offset 58 */ 49 uint32_t Reserved5; /* offset 5c */ 50 uint32_t irq_vector_4; /* offset 60 */ 51 uint32_t Reserved6; /* offset 64 */ 52 uint32_t irq_vector_5; /* offset 68 */ 53 uint32_t Reserved7; /* offset 6c */ 54 uint32_t irq_vector_6; /* offset 70 */ 55 uint32_t Reserved8; /* offset 74 */ 56 uint32_t irq_vector_7; /* offset 78 */ 57 uint32_t Reserved9; /* offset 7c */ 58 uint32_t irq_vector_8; /* offset 80 */ 59 uint32_t Reserved10; /* offset 84 */ 60 uint32_t irq_vector_9; /* offset 88 */ 61 uint32_t Reserved11; /* offset 8c */ 62 uint32_t irq_vector_10; /* offset 90 */ 63 uint32_t Reserved12; /* offset 94 */ 64 uint32_t irq_vector_11; /* offset 98 */ 65 uint32_t Reserved13; /* offset 9c */ 66 uint32_t irq_vector_12; /* offset a0 */ 67 uint32_t Reserved14; /* offset a4 */ 68 uint32_t irq_vector_13; /* offset a8 */ 69 uint32_t Reserved15; /* offset ac */ 70 uint32_t irq_vector_14; /* offset b0 */ 71 uint32_t Reserved16; /* offset b4 */ 72 uint32_t irq_vector_15; /* offset b8 */ 73 uint32_t Reserved17; /* offset bc */ 74 uint32_t fiq_inten; /* offset c0 */ 75 uint32_t fiq_intmask; /* offset c4 */ 76 uint32_t fiq_intforce; /* offset c8 */ 77 uint32_t fiq_rawstatus; /* offset cc */ 78 uint32_t fiq_status; /* offset d0 */ 79 uint32_t fiq_finalstatus; /* offset d4 */ 80 uint32_t irq_plevel; /* offset d8 */ 81 uint32_t Reserved18; /* offset dc */ 82 uint32_t APB_ICTL_COMP_VERSION; /* offset e0 */ 83 uint32_t Reserved19[199]; 84 }; 85 86 #ifdef __cplusplus 87 } 88 #endif 89 90 #endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_DW_H_ */ 91
