1# CAVS interrupt controller configuration
2
3# Copyright (c) 2017 Intel Corporation
4# SPDX-License-Identifier: Apache-2.0
5
6config CAVS_ICTL
7	bool "CAVS Interrupt Logic"
8	default y
9	depends on DT_HAS_INTEL_CAVS_INTC_ENABLED
10	depends on MULTI_LEVEL_INTERRUPTS
11	help
12	  These are 4 in number supporting a max of 32 interrupts each.
13
14if CAVS_ICTL
15
16config CAVS_ISR_TBL_OFFSET
17	int "Offset in the SW ISR Table"
18	default 0
19	help
20	  This indicates the offset in the SW_ISR_TABLE beginning from where
21	  the ISRs for CAVS Interrupt Controller are assigned.
22
23config CAVS_ICTL_0_OFFSET
24	int "Parent interrupt number to which CAVS_0 maps"
25	default 0
26
27config CAVS_ICTL_1_OFFSET
28	int "Parent interrupt number to which CAVS_1 maps"
29	default 0
30
31config CAVS_ICTL_2_OFFSET
32	int "Parent interrupt number to which CAVS_2 maps"
33	default 0
34
35config CAVS_ICTL_3_OFFSET
36	int "Parent interrupt number to which CAVS_3 maps"
37	default 0
38
39config CAVS_ICTL_INIT_PRIORITY
40	int "CAVS ICTL Init priority"
41	default 45
42	help
43	  Cavs Interrupt Logic initialization priority.
44
45endif # CAVS_ICTL
46