1 /*
2  * Copyright (c) 2022 Andes Technology Corporation
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file I2C driver for AndesTech atciic100 IP
9  */
10 #include <errno.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/device.h>
13 #include <soc.h>
14 #include <zephyr/drivers/i2c.h>
15 #include <zephyr/sys/util.h>
16 #include <zephyr/sys/sys_io.h>
17 
18 #define I2C_MAX_COUNT		256
19 #define BURST_CMD_COUNT		1
20 
21 #define RED_IDR			0x00
22 #define REG_CFG			0x10
23 #define REG_INTE		0x14
24 #define REG_STAT		0x18
25 #define REG_ADDR		0x1C
26 #define REG_DATA		0x20
27 #define REG_CTRL		0x24
28 #define REG_CMD			0x28
29 #define REG_SET			0x2C
30 
31 #define I2C_BASE(dev) \
32 	((const struct i2c_atciic100_config * const)(dev)->config)->base
33 
34 #define I2C_CFG(dev)	(I2C_BASE(dev) + REG_CFG)
35 #define I2C_INTE(dev)	(I2C_BASE(dev) + REG_INTE)
36 #define I2C_STAT(dev)	(I2C_BASE(dev) + REG_STAT)
37 #define I2C_ADDR(dev)	(I2C_BASE(dev) + REG_ADDR)
38 #define I2C_CMD(dev)	(I2C_BASE(dev) + REG_CMD)
39 #define I2C_SET(dev)	(I2C_BASE(dev) + REG_SET)
40 #define I2C_DATA(dev)	(I2C_BASE(dev) + REG_DATA)
41 #define I2C_CTRL(dev)	(I2C_BASE(dev) + REG_CTRL)
42 
43 #define TARGET_ADDR_MSK			BIT_MASK(10)
44 #define DATA_MSK			BIT_MASK(8)
45 
46 /* Interrupt Enable Register(RW) */
47 #define IEN_ALL				BIT_MASK(10)
48 #define IEN_CMPL			BIT(9)
49 #define IEN_BYTE_RECV			BIT(8)
50 #define IEN_BYTE_TRANS			BIT(7)
51 #define IEN_START			BIT(6)
52 #define IEN_STOP			BIT(5)
53 #define IEN_ARB_LOSE			BIT(4)
54 #define IEN_ADDR_HIT			BIT(3)
55 #define IEN_FIFO_HALF			BIT(2)
56 #define IEN_FIFO_FULL			BIT(1)
57 #define IEN_FIFO_EMPTY			BIT(0)
58 
59 /* Status Register(RW) */
60 #define STATUS_W1C_ALL			(BIT_MASK(7) << 3)
61 #define STATUS_LINE_SDA			BIT(14)
62 #define STATUS_LINE_SCL			BIT(13)
63 #define STATUS_GEN_CALL			BIT(12)
64 #define STATUS_BUS_BUSY			BIT(11)
65 #define STATUS_ACK			BIT(10)
66 #define STATUS_CMPL			BIT(9)
67 #define STATUS_BYTE_RECV		BIT(8)
68 #define STATUS_BYTE_TRANS		BIT(7)
69 #define STATUS_START			BIT(6)
70 #define STATUS_STOP			BIT(5)
71 #define STATUS_ARB_LOSE			BIT(4)
72 #define STATUS_ADDR_HIT			BIT(3)
73 #define STATUS_FIFO_HALF		BIT(2)
74 #define STATUS_FIFO_FULL		BIT(1)
75 #define STATUS_FIFO_EMPTY		BIT(0)
76 
77 /* Control Register(RW) */
78 #define CTRL_PHASE_START		BIT(12)
79 #define CTRL_PHASE_ADDR			BIT(11)
80 #define CTRL_PHASE_DATA			BIT(10)
81 #define CTRL_PHASE_STOP			BIT(9)
82 #define CTRL_DIR			BIT(8)
83 #define CTRL_DATA_COUNT			BIT_MASK(8)
84 
85 /* Command Register(RW) */
86 #define CMD_MSK				BIT_MASK(3)
87 #define CMD_NO_ACT			(0x0)
88 #define CMD_ISSUE_TRANSACTION		(0x1)
89 #define CMD_ACK				(0x2)
90 #define CMD_NACK			(0x3)
91 #define CMD_CLEAR_FIFO			(0x4)
92 #define CMD_RESET_I2C			(0x5)
93 
94 /* Setup Register(RW) */
95 #define SETUP_T_SUDAT			(BIT_MASK(5) << 24)
96 #define SETUP_T_SP			(BIT_MASK(3) << 21)
97 #define SETUP_T_HDDAT			(BIT_MASK(5) << 16)
98 #define SETUP_T_SCL_RATIO		BIT(13)
99 #define SETUP_T_SCLHI			(BIT_MASK(9) << 4)
100 #define SETUP_DMA_EN			BIT(3)
101 #define SETUP_CONTROLLER		BIT(2)
102 #define SETUP_ADDRESSING		BIT(1)
103 #define SETUP_I2C_EN			BIT(0)
104 
105 #if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 30000000
106 
107 #define SETUP_T_SUDAT_STD		(0x3)
108 #define SETUP_T_SP_STD			(0x1)
109 #define SETUP_T_HDDAT_STD		(5)
110 #define SETUP_T_SCL_RATIO_STD		(0x0)
111 #define SETUP_T_SCLHI_STD		(138)
112 
113 #define SETUP_T_SUDAT_FAST		(0x0)
114 #define SETUP_T_SP_FAST			(0x1)
115 #define SETUP_T_HDDAT_FAST		(5)
116 #define SETUP_T_SCL_RATIO_FAST		(0x1)
117 #define SETUP_T_SCLHI_FAST		(18)
118 
119 #define SETUP_T_SUDAT_FAST_P		(0x0)
120 #define SETUP_T_SP_FAST_P		(0x1)
121 #define SETUP_T_HDDAT_FAST_P		(0x0)
122 #define SETUP_T_SCL_RATIO_FAST_P	(0x1)
123 #define SETUP_T_SCLHI_FAST_P		(6)
124 
125 #elif CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 40000000
126 
127 #define SETUP_T_SUDAT_STD		(0x4)
128 #define SETUP_T_SP_STD			(0x2)
129 #define SETUP_T_HDDAT_STD		(0x6)
130 #define SETUP_T_SCL_RATIO_STD		(0x0)
131 #define SETUP_T_SCLHI_STD		(182)
132 
133 #define SETUP_T_SUDAT_FAST		(0x0)
134 #define SETUP_T_SP_FAST			(0x2)
135 #define SETUP_T_HDDAT_FAST		(0x6)
136 #define SETUP_T_SCL_RATIO_FAST		(0x1)
137 #define SETUP_T_SCLHI_FAST		(23)
138 
139 #define SETUP_T_SUDAT_FAST_P		(0x0)
140 #define SETUP_T_SP_FAST_P		(0x2)
141 #define SETUP_T_HDDAT_FAST_P		(0x0)
142 #define SETUP_T_SCL_RATIO_FAST_P	(0x1)
143 #define SETUP_T_SCLHI_FAST_P		(7)
144 
145 #else
146 
147 #define SETUP_T_SUDAT_STD		(0x9)
148 #define SETUP_T_SP_STD			(0x3)
149 #define SETUP_T_HDDAT_STD		(12)
150 #define SETUP_T_SCL_RATIO_STD		(0x0)
151 #define SETUP_T_SCLHI_STD		(287)
152 
153 #define SETUP_T_SUDAT_FAST		(0x0)
154 #define SETUP_T_SP_FAST			(0x3)
155 #define SETUP_T_HDDAT_FAST		(12)
156 #define SETUP_T_SCL_RATIO_FAST		(0x1)
157 #define SETUP_T_SCLHI_FAST		(38)
158 
159 #define SETUP_T_SUDAT_FAST_P		(0x0)
160 #define SETUP_T_SP_FAST_P		(0x3)
161 #define SETUP_T_HDDAT_FAST_P		(0x0)
162 #define SETUP_T_SCL_RATIO_FAST_P	(0x1)
163 #define SETUP_T_SCLHI_FAST_P		(13)
164 
165 #endif
166 
167 #define SETUP_SPEED_MSK			(SETUP_T_SUDAT		| \
168 					SETUP_T_SP		| \
169 					SETUP_T_HDDAT		| \
170 					SETUP_T_SCL_RATIO	| \
171 					SETUP_T_SCLHI)
172 
173 #define SETUP_SPEED_STD			((SETUP_T_SUDAT_STD << 24)	| \
174 					(SETUP_T_SP_STD  << 21)		| \
175 					(SETUP_T_HDDAT_STD << 16)	| \
176 					(SETUP_T_SCL_RATIO_STD << 13)	| \
177 					(SETUP_T_SCLHI_STD << 4))
178 
179 #define SETUP_SPEED_FAST		((SETUP_T_SUDAT_FAST << 24)	| \
180 					(SETUP_T_SP_FAST  << 21)	| \
181 					(SETUP_T_HDDAT_FAST << 16)	| \
182 					(SETUP_T_SCL_RATIO_FAST << 13)	| \
183 					(SETUP_T_SCLHI_FAST << 4))
184 
185 #define SETUP_SPEED_FAST_PLUS		((SETUP_T_SUDAT_FAST_P << 24)	| \
186 					(SETUP_T_SP_FAST_P  << 21)	| \
187 					(SETUP_T_HDDAT_FAST_P << 16)	| \
188 					(SETUP_T_SCL_RATIO_FAST_P << 13)| \
189 					(SETUP_T_SCLHI_FAST_P << 4))
190 
191 #define MAX_XFER_SZ			(256)
192 
193 enum _i2c_ctrl_reg_item_dir {
194 	I2C_CONTROLLER_TX = 0x0,
195 	I2C_CONTROLLER_RX = 0x1,
196 	I2C_TARGET_TX = 0x1,
197 	I2C_TARGET_RX = 0x0,
198 };
199 
200 /* I2C driver running state */
201 enum _i2c_driver_state {
202 	I2C_DRV_NONE = 0x0,
203 	I2C_DRV_INIT = BIT(0),
204 	I2C_DRV_POWER = BIT(1),
205 	I2C_DRV_CFG_PARAM = BIT(2),
206 	I2C_DRV_CONTROLLER_TX = BIT(3),
207 	I2C_DRV_CONTROLLER_RX = BIT(4),
208 	I2C_DRV_TARGET_TX = BIT(5),
209 	I2C_DRV_TARGET_RX = BIT(6),
210 	I2C_DRV_CONTROLLER_TX_CMPL = BIT(7),
211 	I2C_DRV_CONTROLLER_RX_CMPL = BIT(8),
212 	I2C_DRV_TARGET_TX_CMPL = BIT(9),
213 	I2C_DRV_TARGET_RX_CMPL = BIT(10),
214 };
215 
216 /* brief I2C Status */
217 struct _i2c_status {
218 /* /< Mode: 0=Slave, 1=Master */
219 	uint32_t mode:1;
220 	uint32_t general_call: 1;
221 	uint32_t arbitration_lost : 1;
222 	uint32_t target_ack       : 1;
223 };
224 
225 struct i2c_atciic100_dev_data_t {
226 	struct k_sem			i2c_busy_sem;
227 	volatile uint32_t		driver_state;
228 	uint8_t				*middleware_rx_buf;
229 	uint8_t				*middleware_tx_buf;
230 	uint32_t			fifo_depth;
231 	uint32_t			target_addr;
232 	uint32_t			xfer_wt_num;
233 	uint32_t			xfer_rd_num;
234 	uint32_t			xfered_data_wt_ptr; /* write pointer  */
235 	uint32_t			xfered_data_rd_ptr; /* read pointer  */
236 	volatile struct _i2c_status	status;
237 	const struct i2c_target_callbacks	*target_callbacks;
238 	struct i2c_target_config	*target_config;
239 };
240