1 /* ENC424J600 Stand-alone Ethernet Controller with SPI 2 * 3 * Copyright (c) 2016 Intel Corporation 4 * Copyright (c) 2019 PHYTEC Messtechnik GmbH 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #include <zephyr/kernel.h> 10 #include <zephyr/drivers/gpio.h> 11 #include <zephyr/drivers/spi.h> 12 13 #ifndef _ENC424J600_ 14 #define _ENC424J600_ 15 16 /* Bank 0 Registers */ 17 #define ENC424J600_SFR0_ETXSTL 0x00 18 #define ENC424J600_SFR0_ETXSTH 0x01 19 #define ENC424J600_SFR0_ETXLENL 0x02 20 #define ENC424J600_SFR0_ETXLENH 0x03 21 #define ENC424J600_SFR0_ERXSTL 0x04 22 #define ENC424J600_SFR0_ERXSTH 0x05 23 #define ENC424J600_SFR0_ERXTAILL 0x06 24 #define ENC424J600_SFR0_ERXTAILH 0x07 25 #define ENC424J600_SFR0_ERXHEADL 0x08 26 #define ENC424J600_SFR0_ERXHEADH 0x09 27 #define ENC424J600_SFR0_EDMASTL 0x0A 28 #define ENC424J600_SFR0_EDMASTH 0x0B 29 #define ENC424J600_SFR0_EDMALENL 0x0C 30 #define ENC424J600_SFR0_EDMALENH 0x0D 31 #define ENC424J600_SFR0_EDMADSTL 0x0E 32 #define ENC424J600_SFR0_EDMADSTH 0x0F 33 #define ENC424J600_SFR0_EDMACSL 0x10 34 #define ENC424J600_SFR0_EDMACSH 0x11 35 #define ENC424J600_SFR0_ETXSTATL 0x12 36 #define ENC424J600_SFR0_ETXSTATH 0x13 37 #define ENC424J600_SFR0_ETXWIREL 0x14 38 #define ENC424J600_SFR0_ETXWIREH 0x15 39 /* Common Registers */ 40 #define ENC424J600_SFRX_EUDASTL 0x16 41 #define ENC424J600_SFRX_EUDASTH 0x17 42 #define ENC424J600_SFRX_EUDANDL 0x18 43 #define ENC424J600_SFRX_EUDANDH 0x19 44 #define ENC424J600_SFRX_ESTATL 0x1A 45 #define ENC424J600_SFRX_ESTATH 0x1B 46 #define ENC424J600_SFRX_EIRL 0x1C 47 #define ENC424J600_SFRX_EIRH 0x1D 48 #define ENC424J600_SFRX_ECON1L 0x1E 49 #define ENC424J600_SFRX_ECON1H 0x1F 50 51 /* Bank 1 Registers */ 52 #define ENC424J600_SFR1_EHT1L 0x20 53 #define ENC424J600_SFR1_EHT1H 0x21 54 #define ENC424J600_SFR1_EHT2L 0x22 55 #define ENC424J600_SFR1_EHT2H 0x23 56 #define ENC424J600_SFR1_EHT3L 0x24 57 #define ENC424J600_SFR1_EHT3H 0x25 58 #define ENC424J600_SFR1_EHT4L 0x26 59 #define ENC424J600_SFR1_EHT4H 0x27 60 #define ENC424J600_SFR1_EPMM1L 0x28 61 #define ENC424J600_SFR1_EPMM1H 0x29 62 #define ENC424J600_SFR1_EPMM2L 0x2A 63 #define ENC424J600_SFR1_EPMM2H 0x2B 64 #define ENC424J600_SFR1_EPMM3L 0x2C 65 #define ENC424J600_SFR1_EPMM3H 0x2D 66 #define ENC424J600_SFR1_EPMM4L 0x2E 67 #define ENC424J600_SFR1_EPMM4H 0x2F 68 #define ENC424J600_SFR1_EPMCSL 0x30 69 #define ENC424J600_SFR1_EPMCSH 0x31 70 #define ENC424J600_SFR1_EPMOL 0x32 71 #define ENC424J600_SFR1_EPMOH 0x33 72 #define ENC424J600_SFR1_ERXFCONL 0x34 73 #define ENC424J600_SFR1_ERXFCONH 0x35 74 75 /* Bank 2 Registers */ 76 #define ENC424J600_SFR2_MACON1L 0x40 77 #define ENC424J600_SFR2_MACON1H 0x41 78 #define ENC424J600_SFR2_MACON2L 0x42 79 #define ENC424J600_SFR2_MACON2H 0x43 80 #define ENC424J600_SFR2_MABBIPGL 0x44 81 #define ENC424J600_SFR2_MABBIPGH 0x45 82 #define ENC424J600_SFR2_MAIPGL 0x46 83 #define ENC424J600_SFR2_MAIPGH 0x47 84 #define ENC424J600_SFR2_MACLCONL 0x48 85 #define ENC424J600_SFR2_MACLCONH 0x49 86 #define ENC424J600_SFR2_MAMXFLL 0x4A 87 #define ENC424J600_SFR2_MAMXFLH 0x4B 88 #define ENC424J600_SFR2_MICMDL 0x52 89 #define ENC424J600_SFR2_MICMDH 0x53 90 #define ENC424J600_SFR2_MIREGADRL 0x54 91 #define ENC424J600_SFR2_MIREGADRH 0x55 92 93 94 /* Bank 3 Registers */ 95 #define ENC424J600_SFR3_MAADR3L 0x60 96 #define ENC424J600_SFR3_MAADR3H 0x61 97 #define ENC424J600_SFR3_MAADR2L 0x62 98 #define ENC424J600_SFR3_MAADR2H 0x63 99 #define ENC424J600_SFR3_MAADR1L 0x64 100 #define ENC424J600_SFR3_MAADR1H 0x65 101 #define ENC424J600_SFR3_MIWRL 0x66 102 #define ENC424J600_SFR3_MIWRH 0x67 103 #define ENC424J600_SFR3_MIRDL 0x68 104 #define ENC424J600_SFR3_MIRDH 0x69 105 #define ENC424J600_SFR3_MISTATL 0x6A 106 #define ENC424J600_SFR3_MISTATH 0x6B 107 #define ENC424J600_SFR3_EPAUSL 0x6C 108 #define ENC424J600_SFR3_EPAUSH 0x6D 109 #define ENC424J600_SFR3_ECON2L 0x6E 110 #define ENC424J600_SFR3_ECON2H 0x6F 111 #define ENC424J600_SFR3_ERXWML 0x70 112 #define ENC424J600_SFR3_ERXWMH 0x71 113 #define ENC424J600_SFR3_EIEL 0x72 114 #define ENC424J600_SFR3_EIEH 0x73 115 #define ENC424J600_SFR3_EIDLEDL 0x74 116 #define ENC424J600_SFR3_EIDLEDH 0x75 117 118 /* Unbanked SFRs */ 119 #define ENC424J600_SFR4_EGPDATA 0x80 120 #define ENC424J600_SFR4_ERXDATA 0x82 121 #define ENC424J600_SFR4_EUDADATA 0x84 122 #define ENC424J600_SFR4_EGPRDPTL 0x86 123 #define ENC424J600_SFR4_EGPRDPTH 0x87 124 #define ENC424J600_SFR4_EGPWRPTL 0x88 125 #define ENC424J600_SFR4_EGPWRPTH 0x89 126 #define ENC424J600_SFR4_ERXRDPTL 0x8A 127 #define ENC424J600_SFR4_ERXRDPTH 0x8B 128 #define ENC424J600_SFR4_ERXWRPTL 0x8C 129 #define ENC424J600_SFR4_ERXWRPTH 0x8D 130 #define ENC424J600_SFR4_EUDARDPTL 0x8E 131 #define ENC424J600_SFR4_EUDARDPTH 0x8F 132 #define ENC424J600_SFR4_EUDAWRPTL 0x90 133 #define ENC424J600_SFR4_EUDAWRPTH 0x91 134 135 /* PHY Registers */ 136 #define ENC424J600_PSFR_PHCON1 (BIT(8) | 0x00) 137 #define ENC424J600_PSFR_PHSTAT1 (BIT(8) | 0x01) 138 #define ENC424J600_PSFR_PHANA (BIT(8) | 0x04) 139 #define ENC424J600_PSFR_PHANLPA (BIT(8) | 0x05) 140 #define ENC424J600_PSFR_PHANE (BIT(8) | 0x06) 141 #define ENC424J600_PSFR_PHCON2 (BIT(8) | 0x11) 142 #define ENC424J600_PSFR_PHSTAT2 (BIT(8) | 0x1B) 143 #define ENC424J600_PSFR_PHSTAT3 (BIT(8) | 0x1F) 144 145 /* SPI Instructions */ 146 #define ENC424J600_1BC_B0SEL 0xC0 147 #define ENC424J600_1BC_B1SEL 0xC2 148 #define ENC424J600_1BC_B2SEL 0xC4 149 #define ENC424J600_1BC_B3SEL 0xC6 150 #define ENC424J600_1BC_SETETHRST 0xCA 151 #define ENC424J600_1BC_FCDISABLE 0xE0 152 #define ENC424J600_1BC_FCSINGLE 0xE2 153 #define ENC424J600_1BC_FCMULTIPLE 0xE4 154 #define ENC424J600_1BC_FCCLEAR 0xE6 155 #define ENC424J600_1BC_SETPKTDEC 0xCC 156 #define ENC424J600_1BC_DMASTOP 0xD2 157 #define ENC424J600_1BC_DMACKSUM 0xD8 158 #define ENC424J600_1BC_DMACKSUMS 0xDA 159 #define ENC424J600_1BC_DMACOPY 0xDC 160 #define ENC424J600_1BC_DMACOPYS 0xDE 161 #define ENC424J600_1BC_SETTXRTS 0xD4 162 #define ENC424J600_1BC_ENABLERX 0xE8 163 #define ENC424J600_1BC_DISABLERX 0xEA 164 #define ENC424J600_1BC_SETEIE 0xEC 165 #define ENC424J600_1BC_CLREIE 0xEE 166 #define ENC424J600_2BC_RBSEL 0xC8 167 #define ENC424J600_3BC_WGPRDPT 0x60 168 #define ENC424J600_3BC_RGPRDPT 0x62 169 #define ENC424J600_3BC_WRXRDPT 0x64 170 #define ENC424J600_3BC_RRXRDPT 0x66 171 #define ENC424J600_3BC_WUDARDPT 0x68 172 #define ENC424J600_3BC_RUDARDPT 0x6A 173 #define ENC424J600_3BC_WGPWRPT 0x6C 174 #define ENC424J600_3BC_RGPWRPT 0x6E 175 #define ENC424J600_3BC_WRXWRPT 0x70 176 #define ENC424J600_3BC_RRXWRPT 0x72 177 #define ENC424J600_3BC_WUDAWRPT 0x74 178 #define ENC424J600_3BC_RUDAWRPT 0x76 179 #define ENC424J600_NBC_RCR 0x00 180 #define ENC424J600_NBC_WCR 0x40 181 #define ENC424J600_NBC_RCRU 0x20 182 #define ENC424J600_NBC_WCRU 0x22 183 #define ENC424J600_NBC_BFS 0x80 184 #define ENC424J600_NBC_BFC 0xA0 185 #define ENC424J600_NBC_BFSU 0x24 186 #define ENC424J600_NBC_BFCU 0x26 187 #define ENC424J600_NBC_RGPDATA 0x28 188 #define ENC424J600_NBC_WGPDATA 0x2A 189 #define ENC424J600_NBC_RRXDATA 0x2C 190 #define ENC424J600_NBC_WRXDATA 0x2E 191 #define ENC424J600_NBC_RUDADATA 0x30 192 #define ENC424J600_NBC_WUDADATA 0x32 193 194 /* Significant bits */ 195 #define ENC424J600_MICMD_MIIRD BIT(0) 196 197 #define ENC424J600_MISTAT_BUSY BIT(0) 198 199 #define ENC424J600_ESTAT_RXBUSY BIT(13) 200 #define ENC424J600_ESTAT_CLKRDY BIT(12) 201 #define ENC424J600_ESTAT_PHYLNK BIT(8) 202 203 #define ENC424J600_MACON2_FULDPX BIT(0) 204 205 #define ENC424J600_ERXFCON_CRCEN BIT(6) 206 #define ENC424J600_ERXFCON_RUNTEEN BIT(5) 207 #define ENC424J600_ERXFCON_RUNTEN BIT(4) 208 #define ENC424J600_ERXFCON_UCEN BIT(3) 209 #define ENC424J600_ERXFCON_NOTMEEN BIT(2) 210 #define ENC424J600_ERXFCON_MCEN BIT(1) 211 #define ENC424J600_ERXFCON_BCEN BIT(0) 212 213 #define ENC424J600_PHANA_ADNP BIT(15) 214 #define ENC424J600_PHANA_ADFAULT BIT(13) 215 #define ENC424J600_PHANA_ADPAUS_SYMMETRIC_ONLY BIT(10) 216 #define ENC424J600_PHANA_AD100FD BIT(8) 217 #define ENC424J600_PHANA_AD100 BIT(7) 218 #define ENC424J600_PHANA_AD10FD BIT(6) 219 #define ENC424J600_PHANA_AD10 BIT(5) 220 #define ENC424J600_PHANA_ADIEEE_DEFAULT BIT(0) 221 222 #define ENC424J600_EIE_INTIE BIT(15) 223 #define ENC424J600_EIE_MODEXIE BIT(14) 224 #define ENC424J600_EIE_HASHIE BIT(13) 225 #define ENC424J600_EIE_AESIE BIT(12) 226 #define ENC424J600_EIE_LINKIE BIT(11) 227 #define ENC424J600_EIE_PKTIE BIT(6) 228 #define ENC424J600_EIE_DMAIE BIT(5) 229 #define ENC424J600_EIE_TXIE BIT(3) 230 #define ENC424J600_EIE_TXABTIE BIT(2) 231 #define ENC424J600_EIE_RXABTIE BIT(1) 232 #define ENC424J600_EIE_PCFULIE BIT(0) 233 234 #define ENC424J600_ECON1_PKTDEC BIT(8) 235 #define ENC424J600_ECON1_TXRTS BIT(1) 236 #define ENC424J600_ECON1_RXEN BIT(0) 237 238 #define ENC424J600_ECON2_ETHEN BIT(15) 239 #define ENC424J600_ECON2_STRCH BIT(14) 240 241 #define ENC424J600_EIR_LINKIF BIT(11) 242 #define ENC424J600_EIR_PKTIF BIT(6) 243 #define ENC424J600_EIR_TXIF BIT(3) 244 #define ENC424J600_EIR_TXABTIF BIT(2) 245 #define ENC424J600_EIR_RXABTIF BIT(1) 246 #define ENC424J600_EIR_PCFULIF BIT(0) 247 248 #define ENC424J600_PHCON1_PSLEEP BIT(11) 249 #define ENC424J600_PHCON1_RENEG BIT(9) 250 #define ENC424J600_PHSTAT3_SPDDPX_FD BIT(4) 251 #define ENC424J600_PHSTAT3_SPDDPX_100 BIT(3) 252 #define ENC424J600_PHSTAT3_SPDDPX_10 BIT(2) 253 254 /* Buffer Configuration */ 255 #define ENC424J600_TXSTART 0x0000U 256 #define ENC424J600_TXEND 0x2FFFU 257 #define ENC424J600_RXSTART (ENC424J600_TXEND + 1) 258 #define ENC424J600_RXEND 0x5FFFU 259 #define ENC424J600_EUDAST_DEFAULT 0x6000U 260 #define ENC424J600_EUDAND_DEFAULT (ENC424J600_EUDAST + 1) 261 262 /* Status vectors array size */ 263 #define ENC424J600_RSV_SIZE 6U 264 #define ENC424J600_PTR_NXP_PKT_SIZE 2U 265 266 /* Full-Duplex mode Inter-Packet Gap default value */ 267 #define ENC424J600_MABBIPG_DEFAULT 0x15U 268 269 #define ENC424J600_DEFAULT_NUMOF_RETRIES 3U 270 271 /* Delay for PHY write/read operations (25.6 us) */ 272 #define ENC424J600_PHY_ACCESS_DELAY 26U 273 274 #define ENC424J600_PHY_READY_DELAY 260U 275 276 struct enc424j600_config { 277 struct spi_dt_spec spi; 278 struct gpio_dt_spec interrupt; 279 uint8_t full_duplex; 280 int32_t timeout; 281 }; 282 283 struct enc424j600_runtime { 284 struct net_if *iface; 285 const struct device *dev; 286 287 K_KERNEL_STACK_MEMBER(thread_stack, 288 CONFIG_ETH_ENC424J600_RX_THREAD_STACK_SIZE); 289 290 struct k_thread thread; 291 uint8_t mac_address[6]; 292 struct gpio_callback gpio_cb; 293 struct k_sem tx_rx_sem; 294 struct k_sem int_sem; 295 uint16_t next_pkt_ptr; 296 bool suspended : 1; 297 bool iface_initialized : 1; 298 }; 299 300 #endif /*_ENC424J600_*/ 301
