1 /*
2 * Copyright (c) 2020 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nuvoton_npcx_espi
8
9 #include <assert.h>
10 #include <zephyr/drivers/espi.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/drivers/clock_control.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/dt-bindings/espi/npcx_espi.h>
15 #include <zephyr/kernel.h>
16 #include <zephyr/sys/byteorder.h>
17 #include <zephyr/sys/util.h>
18 #include <soc.h>
19 #include "espi_utils.h"
20 #include "soc_host.h"
21 #include "soc_miwu.h"
22
23 #include <zephyr/logging/log.h>
24 #include <zephyr/irq.h>
25 LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
26
27 struct espi_npcx_config {
28 uintptr_t base;
29 /* clock configuration */
30 struct npcx_clk_cfg clk_cfg;
31 /* mapping table between eSPI reset signal and wake-up input */
32 struct npcx_wui espi_rst_wui;
33 /* pinmux configuration */
34 const struct pinctrl_dev_config *pcfg;
35 };
36
37 struct espi_npcx_data {
38 sys_slist_t callbacks;
39 uint8_t plt_rst_asserted;
40 uint8_t espi_rst_asserted;
41 uint8_t sx_state;
42 #if defined(CONFIG_ESPI_OOB_CHANNEL)
43 struct k_sem oob_rx_lock;
44 #endif
45 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
46 struct k_sem flash_rx_lock;
47 #endif
48 };
49
50 /* Driver convenience defines */
51 #define HAL_INSTANCE(dev) \
52 ((struct espi_reg *)((const struct espi_npcx_config *)(dev)->config)->base)
53
54 /* eSPI channels */
55 #define NPCX_ESPI_CH_PC 0
56 #define NPCX_ESPI_CH_VW 1
57 #define NPCX_ESPI_CH_OOB 2
58 #define NPCX_ESPI_CH_FLASH 3
59 #define NPCX_ESPI_CH_COUNT 4
60 #define NPCX_ESPI_HOST_CH_EN(ch) (ch + 4)
61
62 /* eSPI max supported frequency */
63 #define NPCX_ESPI_MAXFREQ_20 0
64 #define NPCX_ESPI_MAXFREQ_25 1
65 #define NPCX_ESPI_MAXFREQ_33 2
66 #define NPCX_ESPI_MAXFREQ_50 3
67
68 /* Minimum delay before acknowledging a virtual wire */
69 #define NPCX_ESPI_VWIRE_ACK_DELAY 10ul /* 10 us */
70
71 /* OOB channel maximum payload size */
72 #define NPCX_ESPI_OOB_MAX_PAYLOAD 64
73 #define NPCX_OOB_RX_PACKAGE_LEN(hdr) (((hdr & 0xff000000) >> 24) | \
74 ((hdr & 0xf0000) >> 8))
75
76 /* Flash channel maximum payload size */
77 #define NPCX_ESPI_FLASH_MAX_RX_PAYLOAD 64
78 #define NPCX_ESPI_FLASH_MAX_TX_PAYLOAD 16
79
80 /* eSPI cycle type field for OOB and FLASH channels */
81 #define ESPI_FLASH_READ_CYCLE_TYPE 0x00
82 #define ESPI_FLASH_WRITE_CYCLE_TYPE 0x01
83 #define ESPI_FLASH_ERASE_CYCLE_TYPE 0x02
84 #define ESPI_FLASH_SUCCESS_WITH_DATA_CYCLE_TYPE 0x0f
85 #define ESPI_FLASH_SUCCESS_WITHOUT_DATA_CYCLE_TYPE 0x06
86 #define ESPI_FLASH_HEADER_PCKT_SIZE 0x07
87 #define ESPI_FLASH_MAX_TIMEOUT 1000ul /* 1000 ms */
88 #define ESPI_OOB_GET_CYCLE_TYPE 0x21
89 #define ESPI_OOB_TAG 0x00
90 #define ESPI_OOB_MAX_TIMEOUT 500ul /* 500 ms */
91
92 /* eSPI bus interrupt configuration structure and macro function */
93 struct espi_bus_isr {
94 uint8_t status_bit; /* bit order in ESPISTS register */
95 uint8_t int_en_bit; /* bit order in ESPIIE register */
96 uint8_t wake_en_bit; /* bit order in ESPIWE register */
97 void (*bus_isr)(const struct device *dev); /* eSPI bus ISR */
98 };
99
100 #define NPCX_ESPI_BUS_INT_ITEM(event, isr) { \
101 .status_bit = NPCX_ESPISTS_##event, \
102 .int_en_bit = NPCX_ESPIIE_##event##IE, \
103 .wake_en_bit = NPCX_ESPIWE_##event##WE, \
104 .bus_isr = isr }
105
106 /* eSPI Virtual Wire Input (Master-to-Slave) signals configuration structure */
107 struct npcx_vw_in_config {
108 enum espi_vwire_signal sig; /* Virtual Wire signal */
109 uint8_t reg_idx; /* register index for VW signal */
110 uint8_t bitmask; /* VW signal bits-mask */
111 struct npcx_wui vw_wui; /* WUI mapping in MIWU modules for VW signal */
112 };
113
114 /* eSPI Virtual Wire Output (Slave-to-Master) signals configuration structure */
115 struct npcx_vw_out_config {
116 enum espi_vwire_signal sig; /* Virtual Wire signal */
117 uint8_t reg_idx; /* register index for VW signal */
118 uint8_t bitmask; /* VW signal bits-mask */
119 };
120
121 /*
122 * eSPI VW input/Output signal configuration tables. Please refer
123 * npcxn-espi-vws-map.dtsi device tree file for more detail.
124 */
125 static const struct npcx_vw_in_config vw_in_tbl[] = {
126 /* index 02h (In) */
127 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S3, vw_slp_s3),
128 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S4, vw_slp_s4),
129 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S5, vw_slp_s5),
130 /* index 03h (In) */
131 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_STAT, vw_sus_stat),
132 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_PLTRST, vw_plt_rst),
133 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_OOB_RST_WARN, vw_oob_rst_warn),
134 /* index 07h (In) */
135 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_HOST_RST_WARN, vw_host_rst_warn),
136 /* index 41h (In) */
137 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_WARN, vw_sus_warn),
138 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK, vw_sus_pwrdn_ack),
139 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_A, vw_slp_a),
140 /* index 42h (In) */
141 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_LAN, vw_slp_lan),
142 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_WLAN, vw_slp_wlan),
143 };
144
145 static const struct npcx_vw_out_config vw_out_tbl[] = {
146 /* index 04h (Out) */
147 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_OOB_RST_ACK, vw_oob_rst_ack),
148 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_WAKE, vw_wake),
149 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_PME, vw_pme),
150 /* index 05h (Out) */
151 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_BOOT_DONE, vw_slv_boot_done),
152 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_ERR_FATAL, vw_err_fatal),
153 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_ERR_NON_FATAL, vw_err_non_fatal),
154 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_BOOT_STS,
155 vw_slv_boot_sts_with_done),
156 /* index 06h (Out) */
157 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SCI, vw_sci),
158 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SMI, vw_smi),
159 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_HOST_RST_ACK, vw_host_rst_ack),
160 /* index 40h (Out) */
161 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SUS_ACK, vw_sus_ack),
162 };
163
164 /* Virtual wire GPIOs for platform level usage (High at Reset state) */
165 static const struct npcx_vw_out_config vw_out_gpio_tbl1[] = {
166 /* index 50h (Out) */
167 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_GPIO_0, vw_slv_gpio_0),
168 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_GPIO_1, vw_slv_gpio_1),
169 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_GPIO_2, vw_slv_gpio_2),
170 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_GPIO_3, vw_slv_gpio_3),
171 /* index 51h (Out) */
172 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_GPIO_4, vw_slv_gpio_4),
173 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_GPIO_5, vw_slv_gpio_5),
174 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_GPIO_6, vw_slv_gpio_6),
175 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_GPIO_7, vw_slv_gpio_7),
176 };
177
178 /* Callbacks for eSPI bus reset and Virtual Wire signals. */
179 static struct miwu_callback espi_rst_callback;
180 static struct miwu_callback vw_in_callback[ARRAY_SIZE(vw_in_tbl)];
181
182 /* eSPI VW service function forward declarations */
183 static int espi_npcx_receive_vwire(const struct device *dev,
184 enum espi_vwire_signal signal, uint8_t *level);
185 static int espi_npcx_send_vwire(const struct device *dev,
186 enum espi_vwire_signal signal, uint8_t level);
187 static void espi_vw_send_bootload_done(const struct device *dev);
188
189 /* eSPI local initialization functions */
espi_init_wui_callback(const struct device * dev,struct miwu_callback * callback,const struct npcx_wui * wui,miwu_dev_callback_handler_t handler)190 static void espi_init_wui_callback(const struct device *dev,
191 struct miwu_callback *callback, const struct npcx_wui *wui,
192 miwu_dev_callback_handler_t handler)
193 {
194 /* VW signal which has no wake-up input source */
195 if (wui->table == NPCX_MIWU_TABLE_NONE)
196 return;
197
198 /* Install callback function */
199 npcx_miwu_init_dev_callback(callback, wui, handler, dev);
200 npcx_miwu_manage_callback(callback, 1);
201
202 /* Configure MIWU setting and enable its interrupt */
203 npcx_miwu_interrupt_configure(wui, NPCX_MIWU_MODE_EDGE,
204 NPCX_MIWU_TRIG_BOTH);
205 }
206
207 /* eSPI local bus interrupt service functions */
espi_bus_err_isr(const struct device * dev)208 static void espi_bus_err_isr(const struct device *dev)
209 {
210 struct espi_reg *const inst = HAL_INSTANCE(dev);
211 uint32_t err = inst->ESPIERR;
212
213 LOG_ERR("eSPI Bus Error %08X", err);
214 /* Clear error status bits */
215 inst->ESPIERR = err;
216 }
217
espi_bus_inband_rst_isr(const struct device * dev)218 static void espi_bus_inband_rst_isr(const struct device *dev)
219 {
220 ARG_UNUSED(dev);
221 LOG_DBG("%s issued", __func__);
222 }
223
espi_bus_reset_isr(const struct device * dev)224 static void espi_bus_reset_isr(const struct device *dev)
225 {
226 ARG_UNUSED(dev);
227 LOG_DBG("%s issued", __func__);
228 /* Do nothing! This signal is handled in ESPI_RST VW signal ISR */
229 }
230
espi_bus_cfg_update_isr(const struct device * dev)231 static void espi_bus_cfg_update_isr(const struct device *dev)
232 {
233 int chan;
234 struct espi_reg *const inst = HAL_INSTANCE(dev);
235 struct espi_npcx_data *const data = dev->data;
236 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
237 .evt_details = 0,
238 .evt_data = 0 };
239 /* If host enable bits are not sync with ready bits on slave side. */
240 uint8_t chg_mask = GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_HCHANS_FIELD)
241 ^ GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_CHANS_FIELD);
242 chg_mask &= (ESPI_CHANNEL_VWIRE | ESPI_CHANNEL_OOB |
243 ESPI_CHANNEL_FLASH);
244
245 LOG_DBG("ESPI CFG Change Updated! 0x%02X", chg_mask);
246 /*
247 * If host enable/disable channel for VW/OOB/FLASH, EC should follow
248 * except Peripheral channel. It is handled after receiving PLTRST
249 * event separately.
250 */
251 for (chan = NPCX_ESPI_CH_VW; chan < NPCX_ESPI_CH_COUNT; chan++) {
252 /* Channel ready bit isn't sync with enabled bit on host side */
253 if (chg_mask & BIT(chan)) {
254 evt.evt_data = IS_BIT_SET(inst->ESPICFG,
255 NPCX_ESPI_HOST_CH_EN(chan));
256 evt.evt_details = BIT(chan);
257
258 if (evt.evt_data) {
259 inst->ESPICFG |= BIT(chan);
260 } else {
261 inst->ESPICFG &= ~BIT(chan);
262 }
263
264 espi_send_callbacks(&data->callbacks, dev, evt);
265 }
266 }
267 LOG_DBG("ESPI CFG EC Updated! 0x%02X", GET_FIELD(inst->ESPICFG,
268 NPCX_ESPICFG_CHANS_FIELD));
269
270 /* If VW channel is enabled and ready, send bootload done VW signal */
271 if ((chg_mask & BIT(NPCX_ESPI_CH_VW)) && IS_BIT_SET(inst->ESPICFG,
272 NPCX_ESPI_HOST_CH_EN(NPCX_ESPI_CH_VW))) {
273 espi_vw_send_bootload_done(dev);
274 }
275 }
276
277 #if defined(CONFIG_ESPI_OOB_CHANNEL)
espi_bus_oob_rx_isr(const struct device * dev)278 static void espi_bus_oob_rx_isr(const struct device *dev)
279 {
280 struct espi_npcx_data *const data = dev->data;
281
282 LOG_DBG("%s", __func__);
283 k_sem_give(&data->oob_rx_lock);
284 }
285 #endif
286
287 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
espi_bus_flash_rx_isr(const struct device * dev)288 static void espi_bus_flash_rx_isr(const struct device *dev)
289 {
290 struct espi_npcx_data *const data = dev->data;
291
292 LOG_DBG("%s", __func__);
293 k_sem_give(&data->flash_rx_lock);
294 }
295 #endif
296
297 const struct espi_bus_isr espi_bus_isr_tbl[] = {
298 NPCX_ESPI_BUS_INT_ITEM(BERR, espi_bus_err_isr),
299 NPCX_ESPI_BUS_INT_ITEM(IBRST, espi_bus_inband_rst_isr),
300 NPCX_ESPI_BUS_INT_ITEM(ESPIRST, espi_bus_reset_isr),
301 NPCX_ESPI_BUS_INT_ITEM(CFGUPD, espi_bus_cfg_update_isr),
302 #if defined(CONFIG_ESPI_OOB_CHANNEL)
303 NPCX_ESPI_BUS_INT_ITEM(OOBRX, espi_bus_oob_rx_isr),
304 #endif
305 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
306 NPCX_ESPI_BUS_INT_ITEM(FLASHRX, espi_bus_flash_rx_isr),
307 #endif
308 };
309
espi_bus_generic_isr(const struct device * dev)310 static void espi_bus_generic_isr(const struct device *dev)
311 {
312 struct espi_reg *const inst = HAL_INSTANCE(dev);
313 int i;
314 uint32_t mask, status;
315
316 /*
317 * Bit 17 of ESPIIE is reserved. We need to set the same bit in mask
318 * in case bit 17 in ESPISTS of npcx7 is not cleared in ISR.
319 */
320 mask = inst->ESPIIE | (1 << NPCX_ESPISTS_VWUPDW);
321 status = inst->ESPISTS & mask;
322
323 /* Clear pending bits of status register first */
324 inst->ESPISTS = status;
325
326 LOG_DBG("%s: 0x%08X", __func__, status);
327 for (i = 0; i < ARRAY_SIZE(espi_bus_isr_tbl); i++) {
328 struct espi_bus_isr entry = espi_bus_isr_tbl[i];
329
330 if (status & BIT(entry.status_bit)) {
331 if (entry.bus_isr != NULL) {
332 entry.bus_isr(dev);
333 }
334 }
335 }
336 }
337
338 /* eSPI local virtual-wire service functions */
espi_vw_config_input(const struct device * dev,const struct npcx_vw_in_config * config_in)339 static void espi_vw_config_input(const struct device *dev,
340 const struct npcx_vw_in_config *config_in)
341 {
342 struct espi_reg *const inst = HAL_INSTANCE(dev);
343 int idx = config_in->reg_idx;
344
345 /* IE & WE bits are already set? */
346 if (IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_IE) &&
347 IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_WE))
348 return;
349
350 /* Set IE & WE bits in VWEVMS */
351 inst->VWEVMS[idx] |= BIT(NPCX_VWEVMS_IE) | BIT(NPCX_VWEVMS_WE);
352 LOG_DBG("VWEVMS%d 0x%08X", idx, inst->VWEVMS[idx]);
353 }
354
espi_vw_config_output(const struct device * dev,const struct npcx_vw_out_config * config_out)355 static void espi_vw_config_output(const struct device *dev,
356 const struct npcx_vw_out_config *config_out)
357 {
358 struct espi_reg *const inst = HAL_INSTANCE(dev);
359 int idx = config_out->reg_idx;
360 uint8_t valid = GET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_VALID);
361
362 /* Set valid bits for vw signal which we have declared in table. */
363 valid |= config_out->bitmask;
364 SET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_VALID, valid);
365
366 /*
367 * Turn off hardware-wire feature which generates VW events that
368 * connected to hardware signals. We will set it manually by software.
369 */
370 SET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_HW_WIRE, 0);
371
372 LOG_DBG("VWEVSM%d 0x%08X", idx, inst->VWEVSM[idx]);
373 }
374
espi_vw_gpio_config_output(const struct device * dev,const struct npcx_vw_out_config * config_out,uint8_t init_level)375 static void espi_vw_gpio_config_output(const struct device *dev,
376 const struct npcx_vw_out_config *config_out,
377 uint8_t init_level)
378 {
379 struct espi_reg *const inst = HAL_INSTANCE(dev);
380 int idx = config_out->reg_idx;
381 uint8_t valid = GET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_VALID);
382 uint8_t val = GET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_WIRE);
383
384 /* Set valid bits for vw signal which we have declared in table. */
385 valid |= config_out->bitmask;
386 SET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_VALID, valid);
387
388 inst->VWGPSM[idx] |= BIT(NPCX_VWGPSM_INDEX_EN);
389
390 if (init_level) {
391 val |= config_out->bitmask;
392 } else {
393 val &= ~config_out->bitmask;
394 }
395
396 SET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_WIRE, val);
397
398 LOG_DBG("VWEVSM%d 0x%08X", idx, inst->VWGPSM[idx]);
399 }
400
espi_vw_notify_system_state(const struct device * dev,enum espi_vwire_signal signal)401 static void espi_vw_notify_system_state(const struct device *dev,
402 enum espi_vwire_signal signal)
403 {
404 struct espi_npcx_data *const data = dev->data;
405 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
406 uint8_t wire = 0;
407
408 espi_npcx_receive_vwire(dev, signal, &wire);
409 if (!wire) {
410 data->sx_state = signal;
411 }
412
413 evt.evt_details = signal;
414 evt.evt_data = wire;
415 espi_send_callbacks(&data->callbacks, dev, evt);
416 }
417
espi_vw_notify_host_warning(const struct device * dev,enum espi_vwire_signal signal)418 static void espi_vw_notify_host_warning(const struct device *dev,
419 enum espi_vwire_signal signal)
420 {
421 uint8_t wire;
422
423 espi_npcx_receive_vwire(dev, signal, &wire);
424
425 k_busy_wait(NPCX_ESPI_VWIRE_ACK_DELAY);
426 switch (signal) {
427 case ESPI_VWIRE_SIGNAL_HOST_RST_WARN:
428 espi_npcx_send_vwire(dev,
429 ESPI_VWIRE_SIGNAL_HOST_RST_ACK,
430 wire);
431 break;
432 case ESPI_VWIRE_SIGNAL_SUS_WARN:
433 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_SUS_ACK,
434 wire);
435 break;
436 case ESPI_VWIRE_SIGNAL_OOB_RST_WARN:
437 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_OOB_RST_ACK,
438 wire);
439 break;
440 default:
441 break;
442 }
443 }
444
espi_vw_notify_plt_rst(const struct device * dev)445 static void espi_vw_notify_plt_rst(const struct device *dev)
446 {
447 struct espi_npcx_data *const data = dev->data;
448 struct espi_reg *const inst = HAL_INSTANCE(dev);
449 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED,
450 ESPI_VWIRE_SIGNAL_PLTRST, 0
451 };
452 uint8_t wire = 0;
453
454 espi_npcx_receive_vwire(dev, ESPI_VWIRE_SIGNAL_PLTRST, &wire);
455 LOG_DBG("VW_PLT_RST is %d!", wire);
456 if (wire) {
457 /* Set Peripheral Channel ready when PLTRST is de-asserted */
458 inst->ESPICFG |= BIT(NPCX_ESPICFG_PCHANEN);
459 /* Configure all host sub-modules in host domain */
460 npcx_host_init_subs_host_domain();
461 }
462
463 /* PLT_RST will be received several times */
464 if (wire != data->plt_rst_asserted) {
465 data->plt_rst_asserted = wire;
466 evt.evt_data = wire;
467 espi_send_callbacks(&data->callbacks, dev, evt);
468 }
469 }
470
espi_vw_send_bootload_done(const struct device * dev)471 static void espi_vw_send_bootload_done(const struct device *dev)
472 {
473 int ret;
474 uint8_t boot_done;
475
476 ret = espi_npcx_receive_vwire(dev,
477 ESPI_VWIRE_SIGNAL_SLV_BOOT_DONE, &boot_done);
478 LOG_DBG("%s: %d", __func__, boot_done);
479 if (!ret && !boot_done) {
480 /* Send slave boot status bit with done bit at the same time. */
481 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_SLV_BOOT_STS, 1);
482 }
483 }
484
espi_vw_generic_isr(const struct device * dev,struct npcx_wui * wui)485 static void espi_vw_generic_isr(const struct device *dev, struct npcx_wui *wui)
486 {
487 int idx;
488 enum espi_vwire_signal signal;
489
490 LOG_DBG("%s: WUI %d %d %d", __func__, wui->table, wui->group, wui->bit);
491 for (idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
492 if (wui->table == vw_in_tbl[idx].vw_wui.table &&
493 wui->group == vw_in_tbl[idx].vw_wui.group &&
494 wui->bit == vw_in_tbl[idx].vw_wui.bit) {
495 break;
496 }
497 }
498
499 if (idx == ARRAY_SIZE(vw_in_tbl)) {
500 LOG_ERR("Unknown VW event! %d %d %d", wui->table,
501 wui->group, wui->bit);
502 return;
503 }
504
505 signal = vw_in_tbl[idx].sig;
506 if (signal == ESPI_VWIRE_SIGNAL_SLP_S3
507 || signal == ESPI_VWIRE_SIGNAL_SLP_S4
508 || signal == ESPI_VWIRE_SIGNAL_SLP_S5
509 || signal == ESPI_VWIRE_SIGNAL_SLP_A) {
510 espi_vw_notify_system_state(dev, signal);
511 } else if (signal == ESPI_VWIRE_SIGNAL_HOST_RST_WARN
512 || signal == ESPI_VWIRE_SIGNAL_SUS_WARN
513 || signal == ESPI_VWIRE_SIGNAL_OOB_RST_WARN) {
514 espi_vw_notify_host_warning(dev, signal);
515 } else if (signal == ESPI_VWIRE_SIGNAL_PLTRST) {
516 espi_vw_notify_plt_rst(dev);
517 }
518 }
519
espi_vw_espi_rst_isr(const struct device * dev,struct npcx_wui * wui)520 static void espi_vw_espi_rst_isr(const struct device *dev, struct npcx_wui *wui)
521 {
522 struct espi_reg *const inst = HAL_INSTANCE(dev);
523 struct espi_npcx_data *const data = dev->data;
524 struct espi_event evt = { ESPI_BUS_RESET, 0, 0 };
525
526 data->espi_rst_asserted = !IS_BIT_SET(inst->ESPISTS,
527 NPCX_ESPISTS_ESPIRST_LVL);
528 LOG_DBG("eSPI RST asserted is %d!", data->espi_rst_asserted);
529
530 evt.evt_data = data->espi_rst_asserted;
531 espi_send_callbacks(&data->callbacks, dev, evt);
532 }
533
534 /* eSPI api functions */
espi_npcx_configure(const struct device * dev,struct espi_cfg * cfg)535 static int espi_npcx_configure(const struct device *dev, struct espi_cfg *cfg)
536 {
537 struct espi_reg *const inst = HAL_INSTANCE(dev);
538
539 uint8_t max_freq = 0;
540 uint8_t cur_io_mode, io_mode = 0;
541
542 /* Configure eSPI frequency */
543 switch (cfg->max_freq) {
544 case 20:
545 max_freq = NPCX_ESPI_MAXFREQ_20;
546 break;
547 case 25:
548 max_freq = NPCX_ESPI_MAXFREQ_25;
549 break;
550 case 33:
551 max_freq = NPCX_ESPI_MAXFREQ_33;
552 break;
553 case 50:
554 max_freq = NPCX_ESPI_MAXFREQ_50;
555 break;
556 default:
557 return -EINVAL;
558 }
559 SET_FIELD(inst->ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD, max_freq);
560
561 /* Configure eSPI IO mode */
562 io_mode = (cfg->io_caps >> 1);
563 if (io_mode > 3) {
564 return -EINVAL;
565 }
566
567 cur_io_mode = GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_IOMODE_FIELD);
568 if (io_mode != cur_io_mode) {
569 SET_FIELD(inst->ESPICFG, NPCX_ESPICFG_IOMODE_FIELD, io_mode);
570 }
571
572 /* Configure eSPI supported channels */
573 if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL)
574 inst->ESPICFG |= BIT(NPCX_ESPICFG_PCCHN_SUPP);
575
576 if (cfg->channel_caps & ESPI_CHANNEL_VWIRE)
577 inst->ESPICFG |= BIT(NPCX_ESPICFG_VWCHN_SUPP);
578
579 if (cfg->channel_caps & ESPI_CHANNEL_OOB)
580 inst->ESPICFG |= BIT(NPCX_ESPICFG_OOBCHN_SUPP);
581
582 if (cfg->channel_caps & ESPI_CHANNEL_FLASH)
583 inst->ESPICFG |= BIT(NPCX_ESPICFG_FLASHCHN_SUPP);
584
585 LOG_DBG("%s: %d %d ESPICFG: 0x%08X", __func__,
586 max_freq, io_mode, inst->ESPICFG);
587
588 return 0;
589 }
590
espi_npcx_channel_ready(const struct device * dev,enum espi_channel ch)591 static bool espi_npcx_channel_ready(const struct device *dev,
592 enum espi_channel ch)
593 {
594 struct espi_reg *const inst = HAL_INSTANCE(dev);
595 bool sts;
596
597 switch (ch) {
598 case ESPI_CHANNEL_PERIPHERAL:
599 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_PCHANEN);
600 break;
601 case ESPI_CHANNEL_VWIRE:
602 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_VWCHANEN);
603 break;
604 case ESPI_CHANNEL_OOB:
605 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_OOBCHANEN);
606 break;
607 case ESPI_CHANNEL_FLASH:
608 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_FLASHCHANEN);
609 break;
610 default:
611 sts = false;
612 break;
613 }
614
615 return sts;
616 }
617
espi_npcx_send_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t level)618 static int espi_npcx_send_vwire(const struct device *dev,
619 enum espi_vwire_signal signal, uint8_t level)
620 {
621 uint8_t reg_idx, bitmask, sig_idx, val = 0, vw_tbl_size;
622 struct espi_reg *const inst = HAL_INSTANCE(dev);
623 const struct npcx_vw_out_config *vw_tbl;
624 uint32_t reg_val;
625 char *reg_name;
626
627 if (signal >= ESPI_VWIRE_SIGNAL_COUNT) {
628 LOG_ERR("Invalid VW: %d", signal);
629 return -EINVAL;
630 }
631
632 if (signal >= ESPI_VWIRE_SIGNAL_SLV_GPIO_0) {
633 vw_tbl = vw_out_gpio_tbl1;
634 vw_tbl_size = ARRAY_SIZE(vw_out_gpio_tbl1);
635 reg_name = "VWGPSM";
636 } else {
637 vw_tbl = vw_out_tbl;
638 vw_tbl_size = ARRAY_SIZE(vw_out_tbl);
639 reg_name = "VWEVSM";
640 }
641
642 /* Find signal in VW output table */
643 for (sig_idx = 0; sig_idx < vw_tbl_size; sig_idx++)
644 if (vw_tbl[sig_idx].sig == signal)
645 break;
646
647 if (sig_idx == vw_tbl_size) {
648 LOG_ERR("%s signal %d is invalid", __func__, signal);
649 return -EIO;
650 }
651
652 reg_idx = vw_tbl[sig_idx].reg_idx;
653 bitmask = vw_tbl[sig_idx].bitmask;
654
655 /* Get wire field and set/clear wire bit */
656 if (signal >= ESPI_VWIRE_SIGNAL_SLV_GPIO_0) {
657 val = GET_FIELD(inst->VWGPSM[reg_idx], NPCX_VWEVSM_WIRE);
658 } else {
659 val = GET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE);
660 }
661
662 if (level) {
663 val |= bitmask;
664 } else {
665 val &= ~bitmask;
666 }
667
668 if (signal >= ESPI_VWIRE_SIGNAL_SLV_GPIO_0) {
669 SET_FIELD(inst->VWGPSM[reg_idx], NPCX_VWEVSM_WIRE, val);
670 reg_val = inst->VWGPSM[reg_idx];
671 } else {
672 SET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE, val);
673 reg_val = inst->VWEVSM[reg_idx];
674 }
675
676 LOG_DBG("Send VW: %s%d 0x%08X", reg_name, reg_idx, reg_val);
677
678 return 0;
679 }
680
espi_npcx_receive_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t * level)681 static int espi_npcx_receive_vwire(const struct device *dev,
682 enum espi_vwire_signal signal, uint8_t *level)
683 {
684 struct espi_reg *const inst = HAL_INSTANCE(dev);
685 uint8_t reg_idx, bitmask, sig_idx, val;
686
687 /* Find signal in VW input table */
688 for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_in_tbl); sig_idx++)
689 if (vw_in_tbl[sig_idx].sig == signal) {
690 reg_idx = vw_in_tbl[sig_idx].reg_idx;
691 bitmask = vw_in_tbl[sig_idx].bitmask;
692
693 val = GET_FIELD(inst->VWEVMS[reg_idx],
694 NPCX_VWEVMS_WIRE);
695 val &= GET_FIELD(inst->VWEVMS[reg_idx],
696 NPCX_VWEVMS_VALID);
697
698 *level = !!(val & bitmask);
699 return 0;
700 }
701
702 /* Find signal in VW output table */
703 for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_out_tbl); sig_idx++)
704 if (vw_out_tbl[sig_idx].sig == signal) {
705 reg_idx = vw_out_tbl[sig_idx].reg_idx;
706 bitmask = vw_out_tbl[sig_idx].bitmask;
707
708 val = GET_FIELD(inst->VWEVSM[reg_idx],
709 NPCX_VWEVSM_WIRE);
710 val &= GET_FIELD(inst->VWEVSM[reg_idx],
711 NPCX_VWEVSM_VALID);
712 *level = !!(val & bitmask);
713 return 0;
714 }
715
716 LOG_ERR("%s Out of index %d", __func__, signal);
717 return -EIO;
718 }
719
espi_npcx_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)720 static int espi_npcx_manage_callback(const struct device *dev,
721 struct espi_callback *callback, bool set)
722 {
723 struct espi_npcx_data *const data = dev->data;
724
725 return espi_manage_callback(&data->callbacks, callback, set);
726 }
727
espi_npcx_read_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)728 static int espi_npcx_read_lpc_request(const struct device *dev,
729 enum lpc_peripheral_opcode op,
730 uint32_t *data)
731 {
732 ARG_UNUSED(dev);
733
734 return npcx_host_periph_read_request(op, data);
735 }
736
espi_npcx_write_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)737 static int espi_npcx_write_lpc_request(const struct device *dev,
738 enum lpc_peripheral_opcode op,
739 uint32_t *data)
740 {
741 ARG_UNUSED(dev);
742
743 return npcx_host_periph_write_request(op, data);
744 }
745
746 #if defined(CONFIG_ESPI_OOB_CHANNEL)
espi_npcx_send_oob(const struct device * dev,struct espi_oob_packet * pckt)747 static int espi_npcx_send_oob(const struct device *dev,
748 struct espi_oob_packet *pckt)
749 {
750 struct espi_reg *const inst = HAL_INSTANCE(dev);
751 uint8_t *oob_buf = pckt->buf;
752 int sz_oob_tx = pckt->len;
753 int idx_tx_buf;
754 uint32_t oob_data;
755
756 /* Check out of OOB transmitted buffer size */
757 if (sz_oob_tx > NPCX_ESPI_OOB_MAX_PAYLOAD) {
758 LOG_ERR("Out of OOB transmitted buffer: %d", sz_oob_tx);
759 return -EINVAL;
760 }
761
762 /* Check OOB Transmit Queue is empty? */
763 if (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL)) {
764 LOG_ERR("OOB channel is busy");
765 return -EBUSY;
766 }
767
768 /*
769 * GET_OOB header (first 4 bytes) in npcx 32-bits tx buffer
770 *
771 * [24:31] - LEN[0:7] Data length of GET_OOB request package
772 * [20:23] - TAG Tag of GET_OOB
773 * [16:19] - LEN[8:11] Ignore it since max payload is 64 bytes
774 * [8:15] - CYCLE_TYPE Cycle type of GET_OOB
775 * [0:7] - SZ_PACK Package size plus 3 bytes header. (Npcx only)
776 */
777 inst->OOBTXBUF[0] = (sz_oob_tx + 3)
778 | (ESPI_OOB_GET_CYCLE_TYPE << 8)
779 | (ESPI_OOB_TAG << 16)
780 | (sz_oob_tx << 24);
781
782 /* Write GET_OOB data into 32-bits tx buffer in little endian */
783 for (idx_tx_buf = 0; idx_tx_buf < sz_oob_tx/4; idx_tx_buf++,
784 oob_buf += 4)
785 inst->OOBTXBUF[idx_tx_buf + 1] = oob_buf[0]
786 | (oob_buf[1] << 8)
787 | (oob_buf[2] << 16)
788 | (oob_buf[3] << 24);
789
790 /* Write remaining bytes of package */
791 if (sz_oob_tx % 4) {
792 int i;
793
794 oob_data = 0;
795 for (i = 0; i < sz_oob_tx % 4; i++)
796 oob_data |= (oob_buf[i] << (8 * i));
797 inst->OOBTXBUF[idx_tx_buf + 1] = oob_data;
798 }
799
800 /*
801 * Notify host a new OOB packet is ready. Please don't write OOB_FREE
802 * to 1 at the same tiem in case clear it unexpectedly.
803 */
804 oob_data = inst->OOBCTL & ~(BIT(NPCX_OOBCTL_OOB_FREE));
805 oob_data |= BIT(NPCX_OOBCTL_OOB_AVAIL);
806 inst->OOBCTL = oob_data;
807
808 while (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL))
809 ;
810
811 LOG_DBG("%s issued!!", __func__);
812 return 0;
813 }
814
espi_npcx_receive_oob(const struct device * dev,struct espi_oob_packet * pckt)815 static int espi_npcx_receive_oob(const struct device *dev,
816 struct espi_oob_packet *pckt)
817 {
818 struct espi_reg *const inst = HAL_INSTANCE(dev);
819 struct espi_npcx_data *const data = dev->data;
820 uint8_t *oob_buf = pckt->buf;
821 uint32_t oob_data;
822 int idx_rx_buf, sz_oob_rx, ret;
823
824 /* Check eSPI bus status first */
825 if (IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_BERR)) {
826 LOG_ERR("%s: eSPI Bus Error: 0x%08X", __func__, inst->ESPIERR);
827 return -EIO;
828 }
829
830 /* Notify host that OOB received buffer is free now. */
831 inst->OOBCTL |= BIT(NPCX_OOBCTL_OOB_FREE);
832
833 /* Wait until get oob package or timeout */
834 ret = k_sem_take(&data->oob_rx_lock, K_MSEC(ESPI_OOB_MAX_TIMEOUT));
835 if (ret == -EAGAIN) {
836 LOG_ERR("%s: Timeout", __func__);
837 return -ETIMEDOUT;
838 }
839
840 /*
841 * PUT_OOB header (first 4 bytes) in npcx 32-bits rx buffer
842 *
843 * [24:31] - LEN[0:7] Data length of PUT_OOB request package
844 * [20:23] - TAG Tag of PUT_OOB
845 * [16:19] - LEN[8:11] Data length of PUT_OOB request package
846 * [8:15] - CYCLE_TYPE Cycle type of PUT_OOB
847 * [0:7] - SZ_PACK Reserved. (Npcx only)
848 */
849 oob_data = inst->OOBRXBUF[0];
850 /* Get received package length first */
851 sz_oob_rx = NPCX_OOB_RX_PACKAGE_LEN(oob_data);
852
853 /* Check OOB received buffer size */
854 if (sz_oob_rx > NPCX_ESPI_OOB_MAX_PAYLOAD) {
855 LOG_ERR("Out of OOB received buffer: %d", sz_oob_rx);
856 return -EINVAL;
857 }
858
859 /* Set received size to package structure */
860 pckt->len = sz_oob_rx;
861
862 /* Read PUT_OOB data into 32-bits rx buffer in little endian */
863 for (idx_rx_buf = 0; idx_rx_buf < sz_oob_rx/4; idx_rx_buf++) {
864 oob_data = inst->OOBRXBUF[idx_rx_buf + 1];
865
866 *(oob_buf++) = oob_data & 0xFF;
867 *(oob_buf++) = (oob_data >> 8) & 0xFF;
868 *(oob_buf++) = (oob_data >> 16) & 0xFF;
869 *(oob_buf++) = (oob_data >> 24) & 0xFF;
870 }
871
872 /* Read remaining bytes of package */
873 if (sz_oob_rx % 4) {
874 int i;
875
876 oob_data = inst->OOBRXBUF[idx_rx_buf + 1];
877 for (i = 0; i < sz_oob_rx % 4; i++)
878 *(oob_buf++) = (oob_data >> (8 * i)) & 0xFF;
879 }
880 return 0;
881 }
882 #endif
883
884 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_npcx_flash_prepare_tx_header(const struct device * dev,int cyc_type,int flash_addr,int flash_len,int tx_payload)885 static void espi_npcx_flash_prepare_tx_header(const struct device *dev,
886 int cyc_type, int flash_addr, int flash_len, int tx_payload)
887 {
888 struct espi_reg *const inst = HAL_INSTANCE(dev);
889
890 /*
891 * First 3 bytes of flash cycle command header in tx buffer
892 *
893 * [24:31] - LEN[0:7] = n Data length of flash cycle request
894 * [16:23] - LEN[8:15] = 0 Ignore it since max buffer size is 64 bytes
895 * [12:15] - TAG = 0 Tag of flash cycle command is always 0 here
896 * [8:11] - CYCLE_TYPE = 0 Cycle type of flash command
897 * [0:7] - SZ_PACK = 7 Overall tx package size. (Used internally.)
898 */
899 inst->FLASHTXBUF[0] = (flash_len << 24) |
900 (cyc_type << 8) |
901 (tx_payload + ESPI_FLASH_HEADER_PCKT_SIZE);
902
903 /*
904 * Following 4 bytes of tager flash address in tx buffer
905 *
906 * [24:31] - ADDR[0:7] Start address of flash cycle command request
907 * [16:23] - ADDR[15:8]
908 * [8:15] - ADDR[23:16]
909 * [0:7] - ADDR[31:24]
910 */
911 inst->FLASHTXBUF[1] = sys_cpu_to_be32(flash_addr);
912
913 }
914
espi_npcx_flash_parse_completion(const struct device * dev)915 static int espi_npcx_flash_parse_completion(const struct device *dev)
916 {
917 int cycle_type;
918 struct espi_reg *const inst = HAL_INSTANCE(dev);
919
920 /*
921 * First 3 bytes of flash cycle completion header in rx buffer
922 *
923 * [24:31] - LEN[0:7] Data length of flash cycle completion package
924 * [16:23] - LEN[8:15] Ignore it since rx bufer size is 64 bytes
925 * [12:15] - TAG Tag of flash cycle completion package
926 * [8:11] - CYCLE_TYPE Cycle type of flash completion
927 * [0:7] - Reserved
928 */
929 cycle_type = (inst->FLASHRXBUF[0] & 0xff00) >> 8;
930 if (cycle_type == ESPI_FLASH_SUCCESS_WITHOUT_DATA_CYCLE_TYPE) {
931 return 0;
932 }
933
934 return -EIO;
935 }
936
espi_npcx_flash_parse_completion_with_data(const struct device * dev,struct espi_flash_packet * pckt)937 static int espi_npcx_flash_parse_completion_with_data(const struct device *dev,
938 struct espi_flash_packet *pckt)
939 {
940 struct espi_reg *const inst = HAL_INSTANCE(dev);
941 int cycle_type, sz_rx_payload;
942
943 /*
944 * First 3 bytes of flash cycle completion header in rx buffer
945 *
946 * [24:31] - LEN[0:7] Data length of flash cycle completion package
947 * [16:23] - LEN[8:15] Ignore it since rx bufer size is 64 bytes
948 * [12:15] - TAG Tag of flash cycle completion package
949 * [8:11] - CYCLE_TYPE Cycle type of flash completion
950 * [0:7] - Reserved
951 *
952 * The following is flash data/
953 */
954 cycle_type = (inst->FLASHRXBUF[0] & 0xff00) >> 8;
955 sz_rx_payload = inst->FLASHRXBUF[0] >> 24;
956 if (cycle_type == ESPI_FLASH_SUCCESS_WITH_DATA_CYCLE_TYPE) {
957 volatile uint32_t *rx_buf = &inst->FLASHRXBUF[1];
958 uint8_t *buf = pckt->buf;
959 uint32_t data;
960
961 /* Get data from flash RX buffer */
962 for (int i = 0; i < sz_rx_payload / 4; i++, rx_buf++) {
963 data = *rx_buf;
964 for (int j = 0; j < 4; j++, buf++) {
965 *buf = data & 0xff;
966 data = data >> 8;
967 }
968 }
969
970 /* Get remaining bytes */
971 if (sz_rx_payload % 4) {
972 data = *rx_buf;
973 for (int j = 0; j < sz_rx_payload % 4; j++, buf++) {
974 *buf = data & 0xff;
975 data = data >> 8;
976 }
977 }
978
979 return 0;
980 }
981
982 return -EIO;
983 }
984
espi_npcx_flash_read(const struct device * dev,struct espi_flash_packet * pckt)985 static int espi_npcx_flash_read(const struct device *dev,
986 struct espi_flash_packet *pckt)
987 {
988 int ret;
989 struct espi_reg *const inst = HAL_INSTANCE(dev);
990 struct espi_npcx_data *const data = dev->data;
991
992 /* Check out of FLASH received buffer size */
993 if (pckt->len > NPCX_ESPI_FLASH_MAX_RX_PAYLOAD) {
994 LOG_ERR("Out of FLASH transmitted buffer: %d", pckt->len);
995 return -EINVAL;
996 }
997
998 /* Check Flash Transmit Queue is empty? */
999 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1000 LOG_ERR("flash channel is busy");
1001 return -EBUSY;
1002 }
1003
1004 /* Prepare FLASH_READ header in tx buffer */
1005 espi_npcx_flash_prepare_tx_header(dev,
1006 ESPI_FLASH_READ_CYCLE_TYPE,
1007 pckt->flash_addr,
1008 pckt->len,
1009 0);
1010
1011 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1012 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1013
1014 /* Wait until get flash package or timeout */
1015 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1016 if (ret == -EAGAIN) {
1017 LOG_ERR("%s: Timeout", __func__);
1018 return -ETIMEDOUT;
1019 }
1020
1021 return espi_npcx_flash_parse_completion_with_data(dev, pckt);
1022 }
1023
espi_npcx_flash_write(const struct device * dev,struct espi_flash_packet * pckt)1024 static int espi_npcx_flash_write(const struct device *dev,
1025 struct espi_flash_packet *pckt)
1026 {
1027 int ret;
1028 uint32_t tx_data;
1029 struct espi_reg *const inst = HAL_INSTANCE(dev);
1030 struct espi_npcx_data *const data = dev->data;
1031 volatile uint32_t *tx_buf = &inst->FLASHTXBUF[2];
1032 uint8_t *buf = pckt->buf;
1033
1034 /* Check out of FLASH transmitted buffer size */
1035 if (pckt->len > NPCX_ESPI_FLASH_MAX_TX_PAYLOAD) {
1036 LOG_ERR("Out of FLASH transmitted buffer: %d", pckt->len);
1037 return -EINVAL;
1038 }
1039
1040 /* Check Flash Transmit Queue is empty? */
1041 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1042 LOG_ERR("flash channel is busy");
1043 return -EBUSY;
1044 }
1045
1046 /* Prepare FLASH_WRITE header in tx buffer */
1047 espi_npcx_flash_prepare_tx_header(dev,
1048 ESPI_FLASH_WRITE_CYCLE_TYPE,
1049 pckt->flash_addr,
1050 pckt->len,
1051 pckt->len);
1052
1053 /* Put package data to flash TX buffer */
1054 for (int i = 0; i < pckt->len / 4; i++, tx_buf++) {
1055 tx_data = 0;
1056 for (int j = 0; j < 4; j++, buf++) {
1057 tx_data |= (*buf << (j * 8));
1058 }
1059 *tx_buf = tx_data;
1060 }
1061
1062 /* Put remaining bytes to flash TX buffer */
1063 if (pckt->len % 4) {
1064 tx_data = 0;
1065 for (int j = 0; j < pckt->len % 4; j++, buf++) {
1066 tx_data |= (*buf << (j * 8));
1067 }
1068 *tx_buf = tx_data;
1069 }
1070
1071 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1072 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1073
1074 /* Wait until get flash package or timeout */
1075 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1076 if (ret == -EAGAIN) {
1077 LOG_ERR("%s: Timeout", __func__);
1078 return -ETIMEDOUT;
1079 }
1080
1081 /* Parse completion package in rx buffer */
1082 return espi_npcx_flash_parse_completion(dev);
1083 }
1084
espi_npcx_flash_erase(const struct device * dev,struct espi_flash_packet * pckt)1085 static int espi_npcx_flash_erase(const struct device *dev,
1086 struct espi_flash_packet *pckt)
1087 {
1088 int ret;
1089 struct espi_reg *const inst = HAL_INSTANCE(dev);
1090 struct espi_npcx_data *const data = dev->data;
1091
1092 /* Check Flash Transmit Queue is empty? */
1093 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1094 LOG_ERR("flash channel is busy");
1095 return -EBUSY;
1096 }
1097
1098 /* Prepare FLASH_ERASE header in tx buffer */
1099 espi_npcx_flash_prepare_tx_header(dev,
1100 ESPI_FLASH_ERASE_CYCLE_TYPE,
1101 pckt->flash_addr,
1102 pckt->len,
1103 0);
1104
1105 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1106 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1107
1108 /* Wait until get flash package or timeout */
1109 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1110 if (ret == -EAGAIN) {
1111 LOG_ERR("%s: Timeout", __func__);
1112 return -ETIMEDOUT;
1113 }
1114
1115 /* Parse completion package in rx buffer */
1116 return espi_npcx_flash_parse_completion(dev);
1117 }
1118 #endif
1119
1120 /* Platform specific espi module functions */
npcx_espi_enable_interrupts(const struct device * dev)1121 void npcx_espi_enable_interrupts(const struct device *dev)
1122 {
1123 const struct espi_npcx_config *const config = dev->config;
1124
1125 /* Enable eSPI bus interrupt */
1126 irq_enable(DT_INST_IRQN(0));
1127
1128 /* Turn on all VW inputs' MIWU interrupts */
1129 for (int idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
1130 npcx_miwu_irq_enable(&(vw_in_tbl[idx].vw_wui));
1131 }
1132
1133 npcx_miwu_irq_enable(&config->espi_rst_wui);
1134 }
1135
npcx_espi_disable_interrupts(const struct device * dev)1136 void npcx_espi_disable_interrupts(const struct device *dev)
1137 {
1138 const struct espi_npcx_config *const config = dev->config;
1139
1140 /* Disable eSPI bus interrupt */
1141 irq_disable(DT_INST_IRQN(0));
1142
1143 /* Turn off all VW inputs' MIWU interrupts */
1144 for (int idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
1145 npcx_miwu_irq_disable(&(vw_in_tbl[idx].vw_wui));
1146 }
1147
1148 npcx_miwu_irq_disable(&config->espi_rst_wui);
1149 }
1150
1151 /* eSPI driver registration */
1152 static int espi_npcx_init(const struct device *dev);
1153
1154 static const struct espi_driver_api espi_npcx_driver_api = {
1155 .config = espi_npcx_configure,
1156 .get_channel_status = espi_npcx_channel_ready,
1157 .send_vwire = espi_npcx_send_vwire,
1158 .receive_vwire = espi_npcx_receive_vwire,
1159 .manage_callback = espi_npcx_manage_callback,
1160 .read_lpc_request = espi_npcx_read_lpc_request,
1161 .write_lpc_request = espi_npcx_write_lpc_request,
1162 #if defined(CONFIG_ESPI_OOB_CHANNEL)
1163 .send_oob = espi_npcx_send_oob,
1164 .receive_oob = espi_npcx_receive_oob,
1165 #endif
1166 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1167 .flash_read = espi_npcx_flash_read,
1168 .flash_write = espi_npcx_flash_write,
1169 .flash_erase = espi_npcx_flash_erase,
1170 #endif
1171 };
1172
1173 static struct espi_npcx_data espi_npcx_data;
1174
1175 PINCTRL_DT_INST_DEFINE(0);
1176 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
1177 "only one 'nuvoton_npcx_espi' compatible node may be present");
1178
1179 static const struct espi_npcx_config espi_npcx_config = {
1180 .base = DT_INST_REG_ADDR(0),
1181 .espi_rst_wui = NPCX_DT_WUI_ITEM_BY_NAME(0, espi_rst_wui),
1182 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
1183 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
1184 };
1185
1186 DEVICE_DT_INST_DEFINE(0, &espi_npcx_init, NULL,
1187 &espi_npcx_data, &espi_npcx_config,
1188 PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
1189 &espi_npcx_driver_api);
1190
espi_npcx_init(const struct device * dev)1191 static int espi_npcx_init(const struct device *dev)
1192 {
1193 const struct espi_npcx_config *const config = dev->config;
1194 struct espi_npcx_data *const data = dev->data;
1195 struct espi_reg *const inst = HAL_INSTANCE(dev);
1196 const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
1197 int i, ret;
1198
1199 /* If booter doesn't set the host interface type */
1200 if (!NPCX_BOOTER_IS_HIF_TYPE_SET()) {
1201 npcx_host_interface_sel(NPCX_HIF_TYPE_ESPI_SHI);
1202 }
1203
1204 if (!device_is_ready(clk_dev)) {
1205 LOG_ERR("clock control device not ready");
1206 return -ENODEV;
1207 }
1208
1209 /* Turn on eSPI device clock first */
1210 ret = clock_control_on(clk_dev, (clock_control_subsys_t)
1211 &config->clk_cfg);
1212 if (ret < 0) {
1213 LOG_ERR("Turn on eSPI clock fail %d", ret);
1214 return ret;
1215 }
1216
1217 if (IS_ENABLED(CONFIG_ESPI_NPCX_BYPASS_CH_ENABLE_FATAL_ERROR)) {
1218 /* Enable the access to the NPCX_ONLY_ESPI_REG2 register */
1219 inst->NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_UNLOCK_REG2;
1220 inst->NPCX_ONLY_ESPI_REG2 &= ~BIT(NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG);
1221 /* Disable the access to the NPCX_ONLY_ESPI_REG2 register */
1222 inst->NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_LOCK_REG2;
1223 }
1224
1225 /* Enable events which share the same espi bus interrupt */
1226 for (i = 0; i < ARRAY_SIZE(espi_bus_isr_tbl); i++) {
1227 inst->ESPIIE |= BIT(espi_bus_isr_tbl[i].int_en_bit);
1228 inst->ESPIWE |= BIT(espi_bus_isr_tbl[i].wake_en_bit);
1229 }
1230
1231 #if defined(CONFIG_ESPI_OOB_CHANNEL)
1232 k_sem_init(&data->oob_rx_lock, 0, 1);
1233 #endif
1234
1235 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
1236 k_sem_init(&data->flash_rx_lock, 0, 1);
1237 #endif
1238
1239 /* Configure Virtual Wire input signals */
1240 for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++)
1241 espi_vw_config_input(dev, &vw_in_tbl[i]);
1242
1243 /* Configure Virtual Wire output signals */
1244 for (i = 0; i < ARRAY_SIZE(vw_out_tbl); i++)
1245 espi_vw_config_output(dev, &vw_out_tbl[i]);
1246
1247 /* Configure Virtual Wire GPIOs that are output high at reset state */
1248 for (i = 0; i < ARRAY_SIZE(vw_out_gpio_tbl1); i++) {
1249 espi_vw_gpio_config_output(dev, &vw_out_gpio_tbl1[i], 1);
1250 }
1251
1252 /* Configure wake-up input and callback for eSPI VW input signal */
1253 for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++)
1254 espi_init_wui_callback(dev, &vw_in_callback[i],
1255 &vw_in_tbl[i].vw_wui, espi_vw_generic_isr);
1256
1257 /* Configure wake-up input and callback for ESPI_RST signal */
1258 espi_init_wui_callback(dev, &espi_rst_callback,
1259 &config->espi_rst_wui, espi_vw_espi_rst_isr);
1260
1261 /* Configure pin-mux for eSPI bus device */
1262 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1263 if (ret < 0) {
1264 LOG_ERR("eSPI pinctrl setup failed (%d)", ret);
1265 return ret;
1266 }
1267
1268 /* Configure host sub-modules which HW blocks belong to core domain */
1269 npcx_host_init_subs_core_domain(dev, &data->callbacks);
1270
1271 /* eSPI Bus interrupt installation */
1272 IRQ_CONNECT(DT_INST_IRQN(0),
1273 DT_INST_IRQ(0, priority),
1274 espi_bus_generic_isr,
1275 DEVICE_DT_INST_GET(0), 0);
1276
1277 /* Enable eSPI bus interrupt */
1278 irq_enable(DT_INST_IRQN(0));
1279
1280 return 0;
1281 }
1282
