1 /*
2 * Copyright (c) 2019 Intel Corporation
3 * Copyright (c) 2021 Microchip Technology Inc.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT microchip_xec_espi_v2
9
10 #include <zephyr/kernel.h>
11 #include <soc.h>
12 #include <errno.h>
13 #include <zephyr/drivers/espi.h>
14 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
15 #include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
16 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
17 #include <zephyr/logging/log.h>
18 #include <zephyr/sys/sys_io.h>
19 #include <zephyr/sys/util.h>
20 #include <zephyr/irq.h>
21 #include "espi_utils.h"
22 #include "espi_mchp_xec_v2.h"
23
24 /* Minimum delay before acknowledging a virtual wire */
25 #define ESPI_XEC_VWIRE_ACK_DELAY 10ul
26
27 /* Maximum timeout to transmit a virtual wire packet.
28 * 10 ms expressed in multiples of 100us
29 */
30 #define ESPI_XEC_VWIRE_SEND_TIMEOUT 100ul
31
32 #define VW_MAX_GIRQS 2ul
33
34 /* 200ms */
35 #define MAX_OOB_TIMEOUT 200ul
36 /* 1s */
37 #define MAX_FLASH_TIMEOUT 1000ul
38
39 /* While issuing flash erase command, it should be ensured that the transfer
40 * length specified is non-zero.
41 */
42 #define ESPI_FLASH_ERASE_DUMMY 0x01ul
43
44 /* OOB maximum address configuration */
45 #define ESPI_XEC_OOB_ADDR_MSW 0x1ffful
46 #define ESPI_XEC_OOB_ADDR_LSW 0xfffful
47
48 /* OOB Rx length */
49 #define ESPI_XEC_OOB_RX_LEN 0x7f00ul
50
51 /* Espi peripheral has 3 uart ports */
52 #define ESPI_PERIPHERAL_UART_PORT0 0
53 #define ESPI_PERIPHERAL_UART_PORT1 1
54
55 #define UART_DEFAULT_IRQ_POS 2u
56 #define UART_DEFAULT_IRQ BIT(UART_DEFAULT_IRQ_POS)
57
58 LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
59
60 #define ESPI_XEC_REG_BASE(dev) \
61 ((struct espi_iom_regs *)ESPI_XEC_CONFIG(dev)->base_addr)
62
63 #define ESPI_XEC_MSVW_REG_BASE(dev) \
64 ((struct espi_msvw_ar_regs *)(ESPI_XEC_CONFIG(dev)->vw_base_addr))
65
66 #define ESPI_XEC_SMVW_REG_OFS 0x200
67
68 #define ESPI_XEC_SMVW_REG_BASE(dev) \
69 ((struct espi_smvw_ar_regs *) \
70 (ESPI_XEC_CONFIG(dev)->vw_base_addr + ESPI_XEC_SMVW_REG_OFS))
71
72 /* PCR */
73 #define XEC_PCR_REG_BASE \
74 ((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
75
76 /* Microchip canonical virtual wire mapping
77 * ------------------------------------------------------------------------|
78 * VW Idx | VW reg | SRC_ID3 | SRC_ID2 | SRC_ID1 | SRC_ID0 |
79 * ------------------------------------------------------------------------|
80 * System Event Virtual Wires
81 * ------------------------------------------------------------------------|
82 * 2h | MSVW00 | res | SLP_S5# | SLP_S4# | SLP_S3# |
83 * 3h | MSVW01 | res | OOB_RST_WARN | PLTRST# | SUS_STAT# |
84 * 4h | SMVW00 | PME# | WAKE# | res | OOB_RST_ACK |
85 * 5h | SMVW01 | SLV_BOOT_STS | ERR_NONFATAL | ERR_FATAL | SLV_BT_DONE |
86 * 6h | SMVW02 | HOST_RST_ACK | RCIN# | SMI# | SCI# |
87 * 7h | MSVW02 | res | NMIOUT# | SMIOUT# | HOS_RST_WARN|
88 * ------------------------------------------------------------------------|
89 * Platform specific virtual wires
90 * ------------------------------------------------------------------------|
91 * 40h | SMVW03 | res | res | DNX_ACK | SUS_ACK# |
92 * 41h | MSVW03 | SLP_A# | res | SUS_PDNACK| SUS_WARN# |
93 * 42h | MSVW04 | res | res | SLP_WLAN# | SLP_LAN# |
94 * 43h | MSVW05 | generic | generic | generic | generic |
95 * 44h | MSVW06 | generic | generic | generic | generic |
96 * 45h | SMVW04 | generic | generic | generic | generic |
97 * 46h | SMVW05 | generic | generic | generic | generic |
98 * 47h | MSVW07 | res | res | res | HOST_C10 |
99 * 4Ah | MSVW08 | res | res | DNX_WARN | res |
100 * These are configurable by overriding device tree vw routing |
101 * 50h | SMVW06 | ocb_3 | ocb_2 | ocb_1 | ocb_0 |
102 * 51h | SMVW07 | gpio_7 | gpio_6 | gpio_5 | gpio_4 |
103 * 52h | SMVW08 | gpio_11 | gpio_10 | gpio_9 | gpio_8 |
104 */
105 static const struct xec_signal vw_tbl[] = {
106 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_S3, vw_slp_s3_n),
107 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_S4, vw_slp_s4_n),
108 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_S5, vw_slp_s5_n),
109 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_OOB_RST_WARN, vw_oob_rst_warn),
110 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_PLTRST, vw_pltrst_n),
111 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SUS_STAT, vw_sus_stat_n),
112 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_HOST_RST_WARN, vw_host_rst_warn),
113 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_NMIOUT, vw_nmiout_n),
114 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SMIOUT, vw_smiout_n),
115 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_A, vw_slp_a_n),
116 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK, vw_sus_pwrdn_ack),
117 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SUS_WARN, vw_sus_warn_n),
118 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_WLAN, vw_slp_wlan_n),
119 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLP_LAN, vw_slp_lan_n),
120 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_HOST_C10, vw_host_c10),
121 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_DNX_WARN, vw_dnx_warn),
122 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_PME, vw_pme_n),
123 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_WAKE, vw_wake_n),
124 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_OOB_RST_ACK, vw_oob_rst_ack),
125 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_BOOT_STS, vw_slave_boot_status),
126 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_ERR_NON_FATAL, vw_error_non_fatal),
127 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_ERR_FATAL, vw_error_fatal),
128 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_BOOT_DONE, vw_slave_boot_done),
129 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_HOST_RST_ACK, vw_host_rst_ack),
130 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_RST_CPU_INIT, vw_rcin_n),
131 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SMI, vw_smi_n),
132 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SCI, vw_sci_n),
133 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_DNX_ACK, vw_dnx_ack),
134 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SUS_ACK, vw_sus_ack_n),
135 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_0, vw_t2c_gpio_0),
136 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_1, vw_t2c_gpio_1),
137 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_2, vw_t2c_gpio_2),
138 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_3, vw_t2c_gpio_3),
139 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_4, vw_t2c_gpio_4),
140 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_5, vw_t2c_gpio_5),
141 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_6, vw_t2c_gpio_6),
142 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_7, vw_t2c_gpio_7),
143 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_8, vw_t2c_gpio_8),
144 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_9, vw_t2c_gpio_9),
145 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_10, vw_t2c_gpio_10),
146 MCHP_DT_ESPI_VW_ENTRY(ESPI_VWIRE_SIGNAL_SLV_GPIO_11, vw_t2c_gpio_11),
147 };
148
149 /* Buffer size are expressed in bytes */
150 #ifdef CONFIG_ESPI_OOB_CHANNEL
151 static uint32_t target_rx_mem[CONFIG_ESPI_OOB_BUFFER_SIZE >> 2];
152 static uint32_t target_tx_mem[CONFIG_ESPI_OOB_BUFFER_SIZE >> 2];
153 #endif
154 #ifdef CONFIG_ESPI_FLASH_CHANNEL
155 static uint32_t target_mem[CONFIG_ESPI_FLASH_BUFFER_SIZE >> 2];
156 #endif
157
xec_msvw_addr(const struct device * dev,uint8_t vw_index)158 static inline uintptr_t xec_msvw_addr(const struct device *dev,
159 uint8_t vw_index)
160 {
161 uintptr_t vwbase = ESPI_XEC_CONFIG(dev)->vw_base_addr;
162
163 return vwbase + vw_index * sizeof(struct espi_msvw_reg);
164 }
165
xec_smvw_addr(const struct device * dev,uint8_t vw_index)166 static inline uintptr_t xec_smvw_addr(const struct device *dev,
167 uint8_t vw_index)
168 {
169 uintptr_t vwbase = ESPI_XEC_CONFIG(dev)->vw_base_addr;
170
171 vwbase += ESPI_XEC_SMVW_REG_OFS;
172 return vwbase + vw_index * sizeof(struct espi_smvw_reg);
173 }
174
espi_xec_configure(const struct device * dev,struct espi_cfg * cfg)175 static int espi_xec_configure(const struct device *dev, struct espi_cfg *cfg)
176 {
177 struct espi_iom_regs *iom_regs = ESPI_XEC_REG_BASE(dev);
178 uint8_t iomode = 0;
179 uint8_t cap0 = iom_regs->CAP0;
180 uint8_t cap1 = iom_regs->CAP1;
181 uint8_t cur_iomode = (cap1 & MCHP_ESPI_GBL_CAP1_IO_MODE_MASK) >>
182 MCHP_ESPI_GBL_CAP1_IO_MODE_POS;
183
184 /* Set frequency */
185 cap1 &= ~MCHP_ESPI_GBL_CAP1_MAX_FREQ_MASK;
186
187 switch (cfg->max_freq) {
188 case 20:
189 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_20M;
190 break;
191 case 25:
192 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_25M;
193 break;
194 case 33:
195 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_33M;
196 break;
197 case 50:
198 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_50M;
199 break;
200 case 66:
201 cap1 |= MCHP_ESPI_GBL_CAP1_MAX_FREQ_66M;
202 break;
203 default:
204 return -EINVAL;
205 }
206
207 /* Set IO mode */
208 iomode = (cfg->io_caps >> 1);
209 if (iomode > 3) {
210 return -EINVAL;
211 }
212
213 if (iomode != cur_iomode) {
214 cap1 &= ~(MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0 <<
215 MCHP_ESPI_GBL_CAP1_IO_MODE_POS);
216 cap1 |= (iomode << MCHP_ESPI_GBL_CAP1_IO_MODE_POS);
217 }
218
219 /* Validate and translate eSPI API channels to MEC capabilities */
220 cap0 &= ~MCHP_ESPI_GBL_CAP0_MASK;
221 if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) {
222 if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_CHANNEL)) {
223 cap0 |= MCHP_ESPI_GBL_CAP0_PC_SUPP;
224 } else {
225 return -EINVAL;
226 }
227 }
228
229 if (cfg->channel_caps & ESPI_CHANNEL_VWIRE) {
230 if (IS_ENABLED(CONFIG_ESPI_VWIRE_CHANNEL)) {
231 cap0 |= MCHP_ESPI_GBL_CAP0_VW_SUPP;
232 } else {
233 return -EINVAL;
234 }
235 }
236
237 if (cfg->channel_caps & ESPI_CHANNEL_OOB) {
238 if (IS_ENABLED(CONFIG_ESPI_OOB_CHANNEL)) {
239 cap0 |= MCHP_ESPI_GBL_CAP0_OOB_SUPP;
240 } else {
241 return -EINVAL;
242 }
243 }
244
245 if (cfg->channel_caps & ESPI_CHANNEL_FLASH) {
246 if (IS_ENABLED(CONFIG_ESPI_FLASH_CHANNEL)) {
247 cap0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP;
248 } else {
249 LOG_ERR("Flash channel not supported");
250 return -EINVAL;
251 }
252 }
253
254 iom_regs->CAP0 = cap0;
255 iom_regs->CAP1 = cap1;
256
257 /* Activate the eSPI block *.
258 * Need to guarantee that this register is configured before RSMRST#
259 * de-assertion and after pinmux
260 */
261 iom_regs->ACTV = 1;
262 LOG_DBG("eSPI block activated successfully");
263
264 return 0;
265 }
266
espi_xec_channel_ready(const struct device * dev,enum espi_channel ch)267 static bool espi_xec_channel_ready(const struct device *dev,
268 enum espi_channel ch)
269 {
270 struct espi_iom_regs *iom_regs = ESPI_XEC_REG_BASE(dev);
271 bool sts;
272
273 switch (ch) {
274 case ESPI_CHANNEL_PERIPHERAL:
275 sts = iom_regs->PCRDY & MCHP_ESPI_PC_READY;
276 break;
277 case ESPI_CHANNEL_VWIRE:
278 sts = iom_regs->VWRDY & MCHP_ESPI_VW_READY;
279 break;
280 case ESPI_CHANNEL_OOB:
281 sts = iom_regs->OOBRDY & MCHP_ESPI_OOB_READY;
282 break;
283 case ESPI_CHANNEL_FLASH:
284 sts = iom_regs->FCRDY & MCHP_ESPI_FC_READY;
285 break;
286 default:
287 sts = false;
288 break;
289 }
290
291 return sts;
292 }
293
espi_xec_send_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t level)294 static int espi_xec_send_vwire(const struct device *dev,
295 enum espi_vwire_signal signal, uint8_t level)
296 {
297 struct xec_signal signal_info = vw_tbl[signal];
298 uint8_t xec_id = signal_info.xec_reg_idx;
299 uint8_t src_id = signal_info.bit;
300 uint8_t dir;
301 uintptr_t regaddr;
302
303 if ((src_id >= ESPI_VWIRE_SRC_ID_MAX) ||
304 (xec_id >= ESPI_MSVW_IDX_MAX)) {
305 return -EINVAL;
306 }
307
308 if (!(signal_info.flags & BIT(MCHP_DT_ESPI_VW_FLAG_STATUS_POS))) {
309 return -EIO; /* VW not enabled */
310 }
311
312 dir = (signal_info.flags >> MCHP_DT_ESPI_VW_FLAG_DIR_POS) & BIT(0);
313
314 if (dir == ESPI_MASTER_TO_SLAVE) {
315 regaddr = xec_msvw_addr(dev, xec_id);
316
317 sys_write8(level, regaddr + MSVW_BI_SRC0 + src_id);
318 }
319
320 if (dir == ESPI_SLAVE_TO_MASTER) {
321 regaddr = xec_smvw_addr(dev, xec_id);
322
323 sys_write8(level, regaddr + SMVW_BI_SRC0 + src_id);
324
325 /* Ensure eSPI virtual wire packet is transmitted
326 * There is no interrupt, so need to poll register
327 */
328 uint8_t rd_cnt = ESPI_XEC_VWIRE_SEND_TIMEOUT;
329
330 while (sys_read8(regaddr + SMVW_BI_SRC_CHG) && rd_cnt--) {
331 k_busy_wait(100);
332 }
333 }
334
335 return 0;
336 }
337
espi_xec_receive_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t * level)338 static int espi_xec_receive_vwire(const struct device *dev,
339 enum espi_vwire_signal signal,
340 uint8_t *level)
341 {
342 struct xec_signal signal_info = vw_tbl[signal];
343 uint8_t xec_id = signal_info.xec_reg_idx;
344 uint8_t src_id = signal_info.bit;
345 uint8_t dir;
346 uintptr_t regaddr;
347
348 if ((src_id >= ESPI_VWIRE_SRC_ID_MAX) ||
349 (xec_id >= ESPI_SMVW_IDX_MAX) || (level == NULL)) {
350 return -EINVAL;
351 }
352
353 if (!(signal_info.flags & BIT(MCHP_DT_ESPI_VW_FLAG_STATUS_POS))) {
354 return -EIO; /* VW not enabled */
355 }
356
357 dir = (signal_info.flags >> MCHP_DT_ESPI_VW_FLAG_DIR_POS) & BIT(0);
358
359 if (dir == ESPI_MASTER_TO_SLAVE) {
360 regaddr = xec_msvw_addr(dev, xec_id);
361 *level = sys_read8(regaddr + MSVW_BI_SRC0 + src_id) & BIT(0);
362 }
363
364 if (dir == ESPI_SLAVE_TO_MASTER) {
365 regaddr = xec_smvw_addr(dev, xec_id);
366 *level = sys_read8(regaddr + SMVW_BI_SRC0 + src_id) & BIT(0);
367 }
368
369 return 0;
370 }
371
372 #ifdef CONFIG_ESPI_OOB_CHANNEL
espi_xec_send_oob(const struct device * dev,struct espi_oob_packet * pckt)373 static int espi_xec_send_oob(const struct device *dev,
374 struct espi_oob_packet *pckt)
375 {
376 int ret;
377 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
378 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
379 uint8_t err_mask = MCHP_ESPI_OOB_TX_STS_IBERR |
380 MCHP_ESPI_OOB_TX_STS_OVRUN |
381 MCHP_ESPI_OOB_TX_STS_BADREQ;
382
383 LOG_DBG("%s", __func__);
384
385 if (!(regs->OOBTXSTS & MCHP_ESPI_OOB_TX_STS_CHEN)) {
386 LOG_ERR("OOB channel is disabled");
387 return -EIO;
388 }
389
390 if (regs->OOBTXSTS & MCHP_ESPI_OOB_TX_STS_BUSY) {
391 LOG_ERR("OOB channel is busy");
392 return -EBUSY;
393 }
394
395 if (pckt->len > CONFIG_ESPI_OOB_BUFFER_SIZE) {
396 LOG_ERR("insufficient space");
397 return -EINVAL;
398 }
399
400 memcpy(target_tx_mem, pckt->buf, pckt->len);
401
402 regs->OOBTXL = pckt->len;
403 regs->OOBTXC = MCHP_ESPI_OOB_TX_CTRL_START;
404 LOG_DBG("%s %d", __func__, regs->OOBTXL);
405
406 /* Wait until ISR or timeout */
407 ret = k_sem_take(&data->tx_lock, K_MSEC(MAX_OOB_TIMEOUT));
408 if (ret == -EAGAIN) {
409 return -ETIMEDOUT;
410 }
411
412 if (regs->OOBTXSTS & err_mask) {
413 LOG_ERR("Tx failed %x", regs->OOBTXSTS);
414 regs->OOBTXSTS = err_mask;
415 return -EIO;
416 }
417
418 return 0;
419 }
420
espi_xec_receive_oob(const struct device * dev,struct espi_oob_packet * pckt)421 static int espi_xec_receive_oob(const struct device *dev,
422 struct espi_oob_packet *pckt)
423 {
424 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
425 uint8_t err_mask = MCHP_ESPI_OOB_RX_STS_IBERR |
426 MCHP_ESPI_OOB_RX_STS_OVRUN;
427
428 if (regs->OOBRXSTS & err_mask) {
429 return -EIO;
430 }
431
432 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
433 int ret;
434 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
435
436 /* Wait until ISR or timeout */
437 ret = k_sem_take(&data->rx_lock, K_MSEC(MAX_OOB_TIMEOUT));
438 if (ret == -EAGAIN) {
439 return -ETIMEDOUT;
440 }
441 #endif
442 /* Check if buffer passed to driver can fit the received buffer */
443 uint32_t rcvd_len = regs->OOBRXL & MCHP_ESPI_OOB_RX_LEN_MASK;
444
445 if (rcvd_len > pckt->len) {
446 LOG_ERR("space rcvd %d vs %d", rcvd_len, pckt->len);
447 return -EIO;
448 }
449
450 pckt->len = rcvd_len;
451 memcpy(pckt->buf, target_rx_mem, pckt->len);
452 memset(target_rx_mem, 0, pckt->len);
453
454 /* Only after data has been copied from SRAM, indicate channel
455 * is available for next packet
456 */
457 regs->OOBRXC |= MCHP_ESPI_OOB_RX_CTRL_AVAIL;
458
459 return 0;
460 }
461 #endif /* CONFIG_ESPI_OOB_CHANNEL */
462
463 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_xec_flash_read(const struct device * dev,struct espi_flash_packet * pckt)464 static int espi_xec_flash_read(const struct device *dev,
465 struct espi_flash_packet *pckt)
466 {
467 int ret;
468 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
469 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
470 uint32_t err_mask = MCHP_ESPI_FC_STS_IBERR |
471 MCHP_ESPI_FC_STS_FAIL |
472 MCHP_ESPI_FC_STS_OVFL |
473 MCHP_ESPI_FC_STS_BADREQ;
474
475 LOG_DBG("%s", __func__);
476
477 if (!(regs->FCSTS & MCHP_ESPI_FC_STS_CHAN_EN)) {
478 LOG_ERR("Flash channel is disabled");
479 return -EIO;
480 }
481
482 if (pckt->len > CONFIG_ESPI_FLASH_BUFFER_SIZE) {
483 LOG_ERR("Invalid size request");
484 return -EINVAL;
485 }
486
487 regs->FCFA[1] = 0;
488 regs->FCFA[0] = pckt->flash_addr;
489 regs->FCBA[1] = 0;
490 regs->FCBA[0] = (uint32_t)&target_mem[0];
491 regs->FCLEN = pckt->len;
492 regs->FCCTL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_RD0);
493 regs->FCCTL |= MCHP_ESPI_FC_CTRL_START;
494
495 /* Wait until ISR or timeout */
496 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT));
497 if (ret == -EAGAIN) {
498 LOG_ERR("%s timeout", __func__);
499 return -ETIMEDOUT;
500 }
501
502 if (regs->FCSTS & err_mask) {
503 LOG_ERR("%s error %x", __func__, err_mask);
504 regs->FCSTS = err_mask;
505 return -EIO;
506 }
507
508 memcpy(pckt->buf, target_mem, pckt->len);
509
510 return 0;
511 }
512
espi_xec_flash_write(const struct device * dev,struct espi_flash_packet * pckt)513 static int espi_xec_flash_write(const struct device *dev,
514 struct espi_flash_packet *pckt)
515 {
516 int ret;
517 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
518 uint32_t err_mask = MCHP_ESPI_FC_STS_IBERR |
519 MCHP_ESPI_FC_STS_OVRUN |
520 MCHP_ESPI_FC_STS_FAIL |
521 MCHP_ESPI_FC_STS_BADREQ;
522
523 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
524
525 LOG_DBG("%s", __func__);
526
527 if (!(regs->FCSTS & MCHP_ESPI_FC_STS_CHAN_EN)) {
528 LOG_ERR("Flash channel is disabled");
529 return -EIO;
530 }
531
532 if ((regs->FCCFG & MCHP_ESPI_FC_CFG_BUSY)) {
533 LOG_ERR("Flash channel is busy");
534 return -EBUSY;
535 }
536
537 memcpy(target_mem, pckt->buf, pckt->len);
538
539 regs->FCFA[1] = 0;
540 regs->FCFA[0] = pckt->flash_addr;
541 regs->FCBA[1] = 0;
542 regs->FCBA[0] = (uint32_t)&target_mem[0];
543 regs->FCLEN = pckt->len;
544 regs->FCCTL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_WR0);
545 regs->FCCTL |= MCHP_ESPI_FC_CTRL_START;
546
547 /* Wait until ISR or timeout */
548 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT));
549 if (ret == -EAGAIN) {
550 LOG_ERR("%s timeout", __func__);
551 return -ETIMEDOUT;
552 }
553
554 if (regs->FCSTS & err_mask) {
555 LOG_ERR("%s err: %x", __func__, err_mask);
556 regs->FCSTS = err_mask;
557 return -EIO;
558 }
559
560 return 0;
561 }
562
espi_xec_flash_erase(const struct device * dev,struct espi_flash_packet * pckt)563 static int espi_xec_flash_erase(const struct device *dev,
564 struct espi_flash_packet *pckt)
565 {
566 int ret;
567 uint32_t status;
568 uint32_t err_mask = MCHP_ESPI_FC_STS_IBERR |
569 MCHP_ESPI_FC_STS_OVRUN |
570 MCHP_ESPI_FC_STS_FAIL |
571 MCHP_ESPI_FC_STS_BADREQ;
572
573 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
574 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
575
576 LOG_DBG("%s", __func__);
577
578 if (!(regs->FCSTS & MCHP_ESPI_FC_STS_CHAN_EN)) {
579 LOG_ERR("Flash channel is disabled");
580 return -EIO;
581 }
582
583 if ((regs->FCCFG & MCHP_ESPI_FC_CFG_BUSY)) {
584 LOG_ERR("Flash channel is busy");
585 return -EBUSY;
586 }
587
588 /* Clear status register */
589 status = regs->FCSTS;
590 regs->FCSTS = status;
591
592 regs->FCFA[1] = 0;
593 regs->FCFA[0] = pckt->flash_addr;
594 regs->FCLEN = ESPI_FLASH_ERASE_DUMMY;
595 regs->FCCTL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_ERS0);
596 regs->FCCTL |= MCHP_ESPI_FC_CTRL_START;
597
598 /* Wait until ISR or timeout */
599 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT));
600 if (ret == -EAGAIN) {
601 LOG_ERR("%s timeout", __func__);
602 return -ETIMEDOUT;
603 }
604
605 if (regs->FCSTS & err_mask) {
606 LOG_ERR("%s err: %x", __func__, err_mask);
607 regs->FCSTS = err_mask;
608 return -EIO;
609 }
610
611 return 0;
612 }
613 #endif /* CONFIG_ESPI_FLASH_CHANNEL */
614
espi_xec_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)615 static int espi_xec_manage_callback(const struct device *dev,
616 struct espi_callback *callback, bool set)
617 {
618 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
619
620 return espi_manage_callback(&data->callbacks, callback, set);
621 }
622
623 #ifdef CONFIG_ESPI_AUTOMATIC_BOOT_DONE_ACKNOWLEDGE
send_slave_bootdone(const struct device * dev)624 static void send_slave_bootdone(const struct device *dev)
625 {
626 int ret;
627 uint8_t boot_done;
628
629 ret = espi_xec_receive_vwire(dev, ESPI_VWIRE_SIGNAL_SLV_BOOT_DONE,
630 &boot_done);
631 if (!ret && !boot_done) {
632 /* SLAVE_BOOT_DONE & SLAVE_LOAD_STS have to be sent together */
633 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_SLV_BOOT_STS, 1);
634 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_SLV_BOOT_DONE, 1);
635 }
636 }
637 #endif
638
639 #ifdef CONFIG_ESPI_OOB_CHANNEL
espi_init_oob(const struct device * dev)640 static void espi_init_oob(const struct device *dev)
641 {
642 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
643 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
644
645 /* Enable OOB Tx/Rx interrupts */
646 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[oob_up_girq_idx].gid,
647 cfg->irq_info_list[oob_up_girq_idx].gpos);
648 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[oob_dn_girq_idx].gid,
649 cfg->irq_info_list[oob_dn_girq_idx].gpos);
650
651 regs->OOBTXA[1] = 0;
652 regs->OOBRXA[1] = 0;
653 regs->OOBTXA[0] = (uint32_t)&target_tx_mem[0];
654 regs->OOBRXA[0] = (uint32_t)&target_rx_mem[0];
655 regs->OOBRXL = 0x00FF0000;
656
657 /* Enable OOB Tx channel enable change status interrupt */
658 regs->OOBTXIEN |= MCHP_ESPI_OOB_TX_IEN_CHG_EN |
659 MCHP_ESPI_OOB_TX_IEN_DONE;
660
661 /* Enable Rx channel to receive data any time
662 * there are case where OOB is not initiated by a previous OOB Tx
663 */
664 regs->OOBRXIEN |= MCHP_ESPI_OOB_RX_IEN;
665 regs->OOBRXC |= MCHP_ESPI_OOB_RX_CTRL_AVAIL;
666 }
667 #endif
668
669 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_init_flash(const struct device * dev)670 static void espi_init_flash(const struct device *dev)
671 {
672 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
673 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
674
675 LOG_DBG("%s", __func__);
676
677 /* Need to clear status done when ROM boots in MAF */
678 LOG_DBG("%s ESPI_FC_REGS->CFG %X", __func__, regs->FCCFG);
679 regs->FCSTS = MCHP_ESPI_FC_STS_DONE;
680
681 /* Enable interrupts */
682 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[fc_girq_idx].gid,
683 cfg->irq_info_list[fc_girq_idx].gpos);
684 regs->FCIEN |= MCHP_ESPI_FC_IEN_CHG_EN;
685 regs->FCIEN |= MCHP_ESPI_FC_IEN_DONE;
686 }
687 #endif
688
espi_bus_init(const struct device * dev)689 static void espi_bus_init(const struct device *dev)
690 {
691 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
692
693 /* Enable bus interrupts */
694 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[pc_girq_idx].gid,
695 cfg->irq_info_list[pc_girq_idx].gpos);
696 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[rst_girq_idx].gid,
697 cfg->irq_info_list[rst_girq_idx].gpos);
698 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[vw_ch_en_girq_idx].gid,
699 cfg->irq_info_list[vw_ch_en_girq_idx].gpos);
700 }
701
702 /* Clear specified eSPI bus GIRQ status */
xec_espi_bus_intr_clr(const struct device * dev,enum xec_espi_girq_idx idx)703 static int xec_espi_bus_intr_clr(const struct device *dev,
704 enum xec_espi_girq_idx idx)
705 {
706 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
707
708 if (idx >= max_girq_idx) {
709 return -EINVAL;
710 }
711
712 mchp_xec_ecia_girq_src_clr(cfg->irq_info_list[idx].gid,
713 cfg->irq_info_list[idx].gpos);
714
715 return 0;
716 }
717
718 /* Enable/disable specified eSPI bus GIRQ */
xec_espi_bus_intr_ctl(const struct device * dev,enum xec_espi_girq_idx idx,uint8_t enable)719 static int xec_espi_bus_intr_ctl(const struct device *dev,
720 enum xec_espi_girq_idx idx,
721 uint8_t enable)
722 {
723 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
724
725 if (idx >= max_girq_idx) {
726 return -EINVAL;
727 }
728
729 if (enable) {
730 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[idx].gid,
731 cfg->irq_info_list[idx].gpos);
732 } else {
733 mchp_xec_ecia_girq_src_dis(cfg->irq_info_list[idx].gid,
734 cfg->irq_info_list[idx].gpos);
735 }
736
737 return 0;
738 }
739
espi_rst_isr(const struct device * dev)740 static void espi_rst_isr(const struct device *dev)
741 {
742 uint8_t rst_sts;
743 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
744 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
745 struct espi_event evt = { ESPI_BUS_RESET, 0, 0 };
746
747 #ifdef ESPI_XEC_V2_DEBUG
748 data->espi_rst_count++;
749 #endif
750
751 rst_sts = regs->ERIS;
752
753 /* eSPI reset status register is clear on write register */
754 regs->ERIS = MCHP_ESPI_RST_ISTS;
755 /* clear GIRQ latched status */
756 xec_espi_bus_intr_clr(dev, rst_girq_idx);
757
758 if (rst_sts & MCHP_ESPI_RST_ISTS) {
759 if (rst_sts & MCHP_ESPI_RST_ISTS_PIN_RO_HI) {
760 evt.evt_data = 1;
761 } else {
762 evt.evt_data = 0;
763 }
764
765 espi_send_callbacks(&data->callbacks, dev, evt);
766 #ifdef CONFIG_ESPI_OOB_CHANNEL
767 espi_init_oob(dev);
768 #endif
769 #ifdef CONFIG_ESPI_FLASH_CHANNEL
770 espi_init_flash(dev);
771 #endif
772 espi_bus_init(dev);
773 }
774 }
775
776 /* Configure sub devices BAR address if not using default I/O based address
777 * then make its BAR valid.
778 * Refer to microchip eSPI I/O base addresses for default values
779 */
config_sub_devices(const struct device * dev)780 static void config_sub_devices(const struct device *dev)
781 {
782 xec_host_dev_init(dev);
783 }
784
configure_sirq(const struct device * dev)785 static void configure_sirq(const struct device *dev)
786 {
787 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
788
789 #ifdef CONFIG_ESPI_PERIPHERAL_UART
790 switch (CONFIG_ESPI_PERIPHERAL_UART_SOC_MAPPING) {
791 case ESPI_PERIPHERAL_UART_PORT0:
792 regs->SIRQ[SIRQ_UART0] = UART_DEFAULT_IRQ;
793 break;
794 case ESPI_PERIPHERAL_UART_PORT1:
795 regs->SIRQ[SIRQ_UART1] = UART_DEFAULT_IRQ;
796 break;
797 }
798 #endif
799 #ifdef CONFIG_ESPI_PERIPHERAL_8042_KBC
800 regs->SIRQ[SIRQ_KBC_KIRQ] = 1;
801 regs->SIRQ[SIRQ_KBC_MIRQ] = 12;
802 #endif
803 }
804
setup_espi_io_config(const struct device * dev,uint16_t host_address)805 static void setup_espi_io_config(const struct device *dev,
806 uint16_t host_address)
807 {
808 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
809
810 regs->IOHBAR[IOB_IOC] = (host_address << 16) |
811 MCHP_ESPI_IO_BAR_HOST_VALID;
812
813 config_sub_devices(dev);
814 configure_sirq(dev);
815
816 regs->PCSTS = MCHP_ESPI_PC_STS_EN_CHG |
817 MCHP_ESPI_PC_STS_BM_EN_CHG_POS;
818 regs->PCIEN |= MCHP_ESPI_PC_IEN_EN_CHG;
819 regs->PCRDY = 1;
820 }
821
822 /*
823 * Write the interrupt select field of the specified MSVW source.
824 * Each MSVW controls 4 virtual wires.
825 */
xec_espi_vw_intr_ctrl(const struct device * dev,uint8_t msvw_idx,uint8_t src_id,uint8_t intr_mode)826 static int xec_espi_vw_intr_ctrl(const struct device *dev, uint8_t msvw_idx,
827 uint8_t src_id, uint8_t intr_mode)
828 {
829 struct espi_msvw_ar_regs *regs = ESPI_XEC_MSVW_REG_BASE(dev);
830
831
832 if ((msvw_idx >= ESPI_NUM_MSVW) || (src_id > 3)) {
833 return -EINVAL;
834 }
835
836 uintptr_t msvw_addr = (uintptr_t)®s->MSVW[msvw_idx];
837
838 sys_write8(intr_mode, msvw_addr + MSVW_BI_IRQ_SEL0 + src_id);
839
840 return 0;
841 }
842
espi_pc_isr(const struct device * dev)843 static void espi_pc_isr(const struct device *dev)
844 {
845 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
846 uint32_t status = regs->PCSTS;
847 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
848 .evt_details = ESPI_CHANNEL_PERIPHERAL,
849 .evt_data = 0 };
850 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
851
852 LOG_DBG("%s %x", __func__, status);
853 if (status & MCHP_ESPI_PC_STS_BUS_ERR) {
854 LOG_ERR("%s bus error", __func__);
855 regs->PCSTS = MCHP_ESPI_PC_STS_BUS_ERR;
856 }
857
858 if (status & MCHP_ESPI_PC_STS_EN_CHG) {
859 if (status & MCHP_ESPI_PC_STS_EN) {
860 setup_espi_io_config(dev, MCHP_ESPI_IOBAR_INIT_DFLT);
861 }
862
863 regs->PCSTS = MCHP_ESPI_PC_STS_EN_CHG;
864 }
865
866 if (status & MCHP_ESPI_PC_STS_BM_EN_CHG) {
867 if (status & MCHP_ESPI_PC_STS_BM_EN) {
868 evt.evt_data = ESPI_PC_EVT_BUS_MASTER_ENABLE;
869 LOG_WRN("%s BM change %x", __func__, status);
870 espi_send_callbacks(&data->callbacks, dev, evt);
871 }
872
873 regs->PCSTS = MCHP_ESPI_PC_STS_BM_EN_CHG;
874 }
875
876 xec_espi_bus_intr_clr(dev, pc_girq_idx);
877 }
878
espi_vw_chan_en_isr(const struct device * dev)879 static void espi_vw_chan_en_isr(const struct device *dev)
880 {
881 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
882 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
883 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
884 .evt_details = ESPI_CHANNEL_VWIRE,
885 .evt_data = 0 };
886 uint32_t status = regs->VWSTS;
887
888 if (status & MCHP_ESPI_VW_EN_STS_RO) {
889 regs->VWRDY = 1;
890 evt.evt_data = 1;
891 /* VW channel interrupt can disabled at this point */
892 xec_espi_bus_intr_ctl(dev, vw_ch_en_girq_idx, 0);
893
894 #ifdef CONFIG_ESPI_AUTOMATIC_BOOT_DONE_ACKNOWLEDGE
895 send_slave_bootdone(dev);
896 #endif
897 }
898
899 espi_send_callbacks(&data->callbacks, dev, evt);
900
901 xec_espi_bus_intr_clr(dev, vw_ch_en_girq_idx);
902 }
903
904 #ifdef CONFIG_ESPI_OOB_CHANNEL
espi_oob_down_isr(const struct device * dev)905 static void espi_oob_down_isr(const struct device *dev)
906 {
907 uint32_t status;
908 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
909 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
910 #ifdef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
911 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_OOB_RECEIVED,
912 .evt_details = 0,
913 .evt_data = 0 };
914 #endif
915
916 status = regs->OOBRXSTS;
917
918 LOG_DBG("%s %x", __func__, status);
919 if (status & MCHP_ESPI_OOB_RX_STS_DONE) {
920 /* Register is write-on-clear, ensure only 1 bit is affected */
921 regs->OOBRXSTS = MCHP_ESPI_OOB_RX_STS_DONE;
922
923 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
924 k_sem_give(&data->rx_lock);
925 #else
926 evt.evt_details = regs->OOBRXL &
927 MCHP_ESPI_OOB_RX_LEN_MASK;
928 espi_send_callbacks(&data->callbacks, dev, evt);
929 #endif
930 }
931
932 xec_espi_bus_intr_clr(dev, oob_dn_girq_idx);
933 }
934
espi_oob_up_isr(const struct device * dev)935 static void espi_oob_up_isr(const struct device *dev)
936 {
937 uint32_t status;
938 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
939 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
940 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
941 .evt_details = ESPI_CHANNEL_OOB,
942 .evt_data = 0
943 };
944
945 status = regs->OOBTXSTS;
946 LOG_DBG("%s sts:%x", __func__, status);
947
948 if (status & MCHP_ESPI_OOB_TX_STS_DONE) {
949 /* Register is write-on-clear, ensure only 1 bit is affected */
950 status = regs->OOBTXSTS = MCHP_ESPI_OOB_TX_STS_DONE;
951 k_sem_give(&data->tx_lock);
952 }
953
954 if (status & MCHP_ESPI_OOB_TX_STS_CHG_EN) {
955 if (status & MCHP_ESPI_OOB_TX_STS_CHEN) {
956 espi_init_oob(dev);
957 /* Indicate OOB channel is ready to eSPI host */
958 regs->OOBRDY = 1;
959 evt.evt_data = 1;
960 }
961
962 status = regs->OOBTXSTS = MCHP_ESPI_OOB_TX_STS_CHG_EN;
963 espi_send_callbacks(&data->callbacks, dev, evt);
964 }
965
966 xec_espi_bus_intr_clr(dev, oob_up_girq_idx);
967 }
968 #endif
969
970 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_flash_isr(const struct device * dev)971 static void espi_flash_isr(const struct device *dev)
972 {
973 uint32_t status;
974 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
975 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
976 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
977 .evt_details = ESPI_CHANNEL_FLASH,
978 .evt_data = 0,
979 };
980
981 status = regs->FCSTS;
982 LOG_DBG("%s %x", __func__, status);
983
984 if (status & MCHP_ESPI_FC_STS_DONE) {
985 /* Ensure to clear only relevant bit */
986 regs->FCSTS = MCHP_ESPI_FC_STS_DONE;
987
988 k_sem_give(&data->flash_lock);
989 }
990
991 if (status & MCHP_ESPI_FC_STS_CHAN_EN_CHG) {
992 /* Ensure to clear only relevant bit */
993 regs->FCSTS = MCHP_ESPI_FC_STS_CHAN_EN_CHG;
994
995 if (status & MCHP_ESPI_FC_STS_CHAN_EN) {
996 espi_init_flash(dev);
997 /* Indicate flash channel is ready to eSPI master */
998 regs->FCRDY = MCHP_ESPI_FC_READY;
999 evt.evt_data = 1;
1000 }
1001
1002 espi_send_callbacks(&data->callbacks, dev, evt);
1003 }
1004
1005 xec_espi_bus_intr_clr(dev, fc_girq_idx);
1006 }
1007 #endif
1008
1009 /* Send callbacks if enabled and track eSPI host system state */
notify_system_state(const struct device * dev,enum espi_vwire_signal signal)1010 static void notify_system_state(const struct device *dev,
1011 enum espi_vwire_signal signal)
1012 {
1013 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
1014 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
1015 uint8_t status = 0;
1016
1017 espi_xec_receive_vwire(dev, signal, &status);
1018 evt.evt_details = signal;
1019 evt.evt_data = status;
1020 espi_send_callbacks(&data->callbacks, dev, evt);
1021 }
1022
notify_host_warning(const struct device * dev,enum espi_vwire_signal signal)1023 static void notify_host_warning(const struct device *dev,
1024 enum espi_vwire_signal signal)
1025 {
1026 uint8_t status;
1027
1028 espi_xec_receive_vwire(dev, signal, &status);
1029
1030 if (!IS_ENABLED(CONFIG_ESPI_AUTOMATIC_WARNING_ACKNOWLEDGE)) {
1031 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
1032 struct espi_event evt = {ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
1033
1034 evt.evt_details = signal;
1035 evt.evt_data = status;
1036 espi_send_callbacks(&data->callbacks, dev, evt);
1037 } else {
1038 k_busy_wait(ESPI_XEC_VWIRE_ACK_DELAY);
1039 /* Some flows are dependent on awareness of client's driver
1040 * about these warnings in such cases these automatic response
1041 * should not be enabled.
1042 */
1043 switch (signal) {
1044 case ESPI_VWIRE_SIGNAL_HOST_RST_WARN:
1045 espi_xec_send_vwire(dev,
1046 ESPI_VWIRE_SIGNAL_HOST_RST_ACK,
1047 status);
1048 break;
1049 case ESPI_VWIRE_SIGNAL_SUS_WARN:
1050 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_SUS_ACK,
1051 status);
1052 break;
1053 case ESPI_VWIRE_SIGNAL_OOB_RST_WARN:
1054 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_OOB_RST_ACK,
1055 status);
1056 break;
1057 case ESPI_VWIRE_SIGNAL_DNX_WARN:
1058 espi_xec_send_vwire(dev, ESPI_VWIRE_SIGNAL_DNX_ACK,
1059 status);
1060 break;
1061 default:
1062 break;
1063 }
1064 }
1065 }
1066
notify_vw_status(const struct device * dev,enum espi_vwire_signal signal)1067 static void notify_vw_status(const struct device *dev,
1068 enum espi_vwire_signal signal)
1069 {
1070 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
1071 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
1072 uint8_t status = 0;
1073
1074 espi_xec_receive_vwire(dev, signal, &status);
1075 evt.evt_details = signal;
1076 evt.evt_data = status;
1077 espi_send_callbacks(&data->callbacks, dev, evt);
1078 }
1079
1080 /*
1081 * VW handlers must have signature
1082 * typedef void (*mchp_xec_ecia_callback_t) (int girq_id, int src, void *user)
1083 * where parameter user is a pointer to const struct device
1084 * These handlers are registered to their respective GIRQ child device of the
1085 * ECIA driver.
1086 */
1087
vw_slp3_handler(int girq_id,int src,void * user)1088 static void vw_slp3_handler(int girq_id, int src, void *user)
1089 {
1090 const struct device *dev = (const struct device *)user;
1091
1092 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SLP_S3);
1093 }
1094
vw_slp4_handler(int girq_id,int src,void * user)1095 static void vw_slp4_handler(int girq_id, int src, void *user)
1096 {
1097 const struct device *dev = (const struct device *)user;
1098
1099 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SLP_S4);
1100 }
1101
vw_slp5_handler(int girq_id,int src,void * user)1102 static void vw_slp5_handler(int girq_id, int src, void *user)
1103 {
1104 const struct device *dev = (const struct device *)user;
1105
1106 notify_system_state(dev, ESPI_VWIRE_SIGNAL_SLP_S5);
1107 }
1108
vw_host_rst_warn_handler(int girq_id,int src,void * user)1109 static void vw_host_rst_warn_handler(int girq_id, int src, void *user)
1110 {
1111 const struct device *dev = (const struct device *)user;
1112
1113 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_HOST_RST_WARN);
1114 }
1115
vw_sus_warn_handler(int girq_id,int src,void * user)1116 static void vw_sus_warn_handler(int girq_id, int src, void *user)
1117 {
1118 const struct device *dev = (const struct device *)user;
1119
1120 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_SUS_WARN);
1121 }
1122
vw_oob_rst_handler(int girq_id,int src,void * user)1123 static void vw_oob_rst_handler(int girq_id, int src, void *user)
1124 {
1125 const struct device *dev = (const struct device *)user;
1126
1127 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_OOB_RST_WARN);
1128 }
1129
vw_sus_pwrdn_ack_handler(int girq_id,int src,void * user)1130 static void vw_sus_pwrdn_ack_handler(int girq_id, int src, void *user)
1131 {
1132 const struct device *dev = (const struct device *)user;
1133
1134 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK);
1135 }
1136
vw_sus_slp_a_handler(int girq_id,int src,void * user)1137 static void vw_sus_slp_a_handler(int girq_id, int src, void *user)
1138 {
1139 const struct device *dev = (const struct device *)user;
1140
1141 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_SLP_A);
1142 }
1143
vw_sus_dnx_warn_handler(int girq_id,int src,void * user)1144 static void vw_sus_dnx_warn_handler(int girq_id, int src, void *user)
1145 {
1146 const struct device *dev = (const struct device *)user;
1147
1148 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_DNX_WARN);
1149 }
1150
vw_pltrst_handler(int girq_id,int src,void * user)1151 static void vw_pltrst_handler(int girq_id, int src, void *user)
1152 {
1153 const struct device *dev = (const struct device *)user;
1154 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
1155 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED,
1156 ESPI_VWIRE_SIGNAL_PLTRST, 0
1157 };
1158 uint8_t status = 0;
1159
1160 espi_xec_receive_vwire(dev, ESPI_VWIRE_SIGNAL_PLTRST, &status);
1161 if (status) {
1162 setup_espi_io_config(dev, MCHP_ESPI_IOBAR_INIT_DFLT);
1163 }
1164
1165 evt.evt_data = status;
1166 espi_send_callbacks(&data->callbacks, dev, evt);
1167 }
1168
vw_sus_stat_handler(int girq_id,int src,void * user)1169 static void vw_sus_stat_handler(int girq_id, int src, void *user)
1170 {
1171 const struct device *dev = (const struct device *)user;
1172
1173 notify_host_warning(dev, ESPI_VWIRE_SIGNAL_SUS_STAT);
1174 }
1175
vw_slp_wlan_handler(int girq_id,int src,void * user)1176 static void vw_slp_wlan_handler(int girq_id, int src, void *user)
1177 {
1178 const struct device *dev = (const struct device *)user;
1179
1180 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_SLP_WLAN);
1181 }
1182
vw_slp_lan_handler(int girq_id,int src,void * user)1183 static void vw_slp_lan_handler(int girq_id, int src, void *user)
1184 {
1185 const struct device *dev = (const struct device *)user;
1186
1187 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_SLP_LAN);
1188 }
1189
vw_host_c10_handler(int girq_id,int src,void * user)1190 static void vw_host_c10_handler(int girq_id, int src, void *user)
1191 {
1192 const struct device *dev = (const struct device *)user;
1193
1194 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_HOST_C10);
1195 }
1196
vw_nmiout_handler(int girq_id,int src,void * user)1197 static void vw_nmiout_handler(int girq_id, int src, void *user)
1198 {
1199 const struct device *dev = (const struct device *)user;
1200
1201 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_NMIOUT);
1202 }
1203
vw_smiout_handler(int girq_id,int src,void * user)1204 static void vw_smiout_handler(int girq_id, int src, void *user)
1205 {
1206 const struct device *dev = (const struct device *)user;
1207
1208 notify_vw_status(dev, ESPI_VWIRE_SIGNAL_SMIOUT);
1209 }
1210
1211 const struct espi_vw_isr m2s_vwires_isr[] = {
1212 {ESPI_VWIRE_SIGNAL_SLP_S3, MCHP_MSVW00_GIRQ,
1213 MCHP_MSVW00_SRC0_GIRQ_POS, vw_slp3_handler},
1214 {ESPI_VWIRE_SIGNAL_SLP_S4, MCHP_MSVW00_GIRQ,
1215 MCHP_MSVW00_SRC1_GIRQ_POS, vw_slp4_handler},
1216 {ESPI_VWIRE_SIGNAL_SLP_S5, MCHP_MSVW00_GIRQ,
1217 MCHP_MSVW00_SRC2_GIRQ_POS, vw_slp5_handler},
1218 {ESPI_VWIRE_SIGNAL_OOB_RST_WARN, MCHP_MSVW01_GIRQ,
1219 MCHP_MSVW01_SRC2_GIRQ_POS, vw_oob_rst_handler},
1220 {ESPI_VWIRE_SIGNAL_PLTRST, MCHP_MSVW01_GIRQ,
1221 MCHP_MSVW01_SRC1_GIRQ_POS, vw_pltrst_handler},
1222 {ESPI_VWIRE_SIGNAL_SUS_STAT, MCHP_MSVW01_GIRQ,
1223 MCHP_MSVW01_SRC0_GIRQ_POS, vw_sus_stat_handler},
1224 {ESPI_VWIRE_SIGNAL_HOST_RST_WARN, MCHP_MSVW02_GIRQ,
1225 MCHP_MSVW02_SRC0_GIRQ_POS, vw_host_rst_warn_handler},
1226 {ESPI_VWIRE_SIGNAL_NMIOUT, MCHP_MSVW02_GIRQ,
1227 MCHP_MSVW02_SRC1_GIRQ_POS, vw_nmiout_handler},
1228 {ESPI_VWIRE_SIGNAL_SMIOUT, MCHP_MSVW02_GIRQ,
1229 MCHP_MSVW02_SRC2_GIRQ_POS, vw_smiout_handler},
1230 {ESPI_VWIRE_SIGNAL_SLP_A, MCHP_MSVW03_GIRQ,
1231 MCHP_MSVW03_SRC3_GIRQ_POS, vw_sus_slp_a_handler},
1232 {ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK, MCHP_MSVW03_GIRQ,
1233 MCHP_MSVW03_SRC1_GIRQ_POS, vw_sus_pwrdn_ack_handler},
1234 {ESPI_VWIRE_SIGNAL_SUS_WARN, MCHP_MSVW03_GIRQ,
1235 MCHP_MSVW03_SRC0_GIRQ_POS, vw_sus_warn_handler},
1236 {ESPI_VWIRE_SIGNAL_SLP_WLAN, MCHP_MSVW04_GIRQ,
1237 MCHP_MSVW04_SRC1_GIRQ_POS, vw_slp_wlan_handler},
1238 {ESPI_VWIRE_SIGNAL_SLP_LAN, MCHP_MSVW04_GIRQ,
1239 MCHP_MSVW04_SRC0_GIRQ_POS, vw_slp_lan_handler},
1240 {ESPI_VWIRE_SIGNAL_HOST_C10, MCHP_MSVW07_GIRQ,
1241 MCHP_MSVW07_SRC0_GIRQ_POS, vw_host_c10_handler},
1242 {ESPI_VWIRE_SIGNAL_DNX_WARN, MCHP_MSVW08_GIRQ,
1243 MCHP_MSVW08_SRC1_GIRQ_POS, vw_sus_dnx_warn_handler},
1244 };
1245
1246 static int espi_xec_init(const struct device *dev);
1247
1248 static const struct espi_driver_api espi_xec_driver_api = {
1249 .config = espi_xec_configure,
1250 .get_channel_status = espi_xec_channel_ready,
1251 .send_vwire = espi_xec_send_vwire,
1252 .receive_vwire = espi_xec_receive_vwire,
1253 #ifdef CONFIG_ESPI_OOB_CHANNEL
1254 .send_oob = espi_xec_send_oob,
1255 .receive_oob = espi_xec_receive_oob,
1256 #endif
1257 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1258 .flash_read = espi_xec_flash_read,
1259 .flash_write = espi_xec_flash_write,
1260 .flash_erase = espi_xec_flash_erase,
1261 #endif
1262 .manage_callback = espi_xec_manage_callback,
1263 .read_lpc_request = espi_xec_read_lpc_request,
1264 .write_lpc_request = espi_xec_write_lpc_request,
1265 };
1266
1267 static struct espi_xec_data espi_xec_data_var;
1268
1269 /* n = node-id, p = property, i = index */
1270 #define XEC_IRQ_INFO(n, p, i) \
1271 { \
1272 .gid = MCHP_XEC_ECIA_GIRQ(DT_PROP_BY_IDX(n, p, i)), \
1273 .gpos = MCHP_XEC_ECIA_GIRQ_POS(DT_PROP_BY_IDX(n, p, i)), \
1274 .anid = MCHP_XEC_ECIA_NVIC_AGGR(DT_PROP_BY_IDX(n, p, i)), \
1275 .dnid = MCHP_XEC_ECIA_NVIC_DIRECT(DT_PROP_BY_IDX(n, p, i)), \
1276 },
1277
1278 static const struct espi_xec_irq_info espi_xec_irq_info_0[] = {
1279 DT_FOREACH_PROP_ELEM(DT_NODELABEL(espi0), girqs, XEC_IRQ_INFO)
1280 };
1281
1282 /* pin control structure(s) */
1283 PINCTRL_DT_INST_DEFINE(0);
1284
1285 static const struct espi_xec_config espi_xec_config = {
1286 .base_addr = DT_INST_REG_ADDR(0),
1287 .vw_base_addr = DT_INST_REG_ADDR_BY_NAME(0, vw),
1288 .pcr_idx = DT_INST_PROP_BY_IDX(0, pcrs, 0),
1289 .pcr_bitpos = DT_INST_PROP_BY_IDX(0, pcrs, 1),
1290 .irq_info_size = ARRAY_SIZE(espi_xec_irq_info_0),
1291 .irq_info_list = espi_xec_irq_info_0,
1292 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
1293 };
1294
1295 DEVICE_DT_INST_DEFINE(0, &espi_xec_init, NULL,
1296 &espi_xec_data_var, &espi_xec_config,
1297 PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
1298 &espi_xec_driver_api);
1299
1300 /*
1301 * Connect ESPI bus interrupt handlers: ESPI_RESET and channels.
1302 * MEC172x hardware fixed SAF interrupt routing bug. SAF driver
1303 * will connect its direct mode interrupt handler(s) on this GIRQ.
1304 */
espi_xec_connect_irqs(const struct device * dev)1305 static void espi_xec_connect_irqs(const struct device *dev)
1306 {
1307 ARG_UNUSED(dev);
1308
1309 /* eSPI Reset */
1310 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 7, irq),
1311 DT_INST_IRQ_BY_IDX(0, 7, priority),
1312 espi_rst_isr,
1313 DEVICE_DT_INST_GET(0), 0);
1314 irq_enable(DT_INST_IRQ_BY_IDX(0, 7, irq));
1315
1316 /* eSPI Virtual wire channel enable change ISR */
1317 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 8, irq),
1318 DT_INST_IRQ_BY_IDX(0, 8, priority),
1319 espi_vw_chan_en_isr,
1320 DEVICE_DT_INST_GET(0), 0);
1321 irq_enable(DT_INST_IRQ_BY_IDX(0, 8, irq));
1322
1323 /* eSPI Peripheral Channel */
1324 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 0, irq),
1325 DT_INST_IRQ_BY_IDX(0, 0, priority),
1326 espi_pc_isr,
1327 DEVICE_DT_INST_GET(0), 0);
1328 irq_enable(DT_INST_IRQ_BY_IDX(0, 0, irq));
1329
1330 #ifdef CONFIG_ESPI_OOB_CHANNEL
1331 /* eSPI OOB Upstream direction */
1332 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 4, irq),
1333 DT_INST_IRQ_BY_IDX(0, 4, priority),
1334 espi_oob_up_isr,
1335 DEVICE_DT_INST_GET(0), 0);
1336 irq_enable(DT_INST_IRQ_BY_IDX(0, 4, irq));
1337
1338 /* eSPI OOB Channel Downstream direction */
1339 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 5, irq),
1340 DT_INST_IRQ_BY_IDX(0, 5, priority),
1341 espi_oob_down_isr,
1342 DEVICE_DT_INST_GET(0), 0);
1343 irq_enable(DT_INST_IRQ_BY_IDX(0, 5, irq));
1344 #endif
1345
1346 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1347 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 6, irq),
1348 DT_INST_IRQ_BY_IDX(0, 6, priority),
1349 espi_flash_isr,
1350 DEVICE_DT_INST_GET(0), 0);
1351 irq_enable(DT_INST_IRQ_BY_IDX(0, 6, irq));
1352 #endif
1353 }
1354
1355 /* MSVW is a 96-bit register and SMVW is a 64-bit register.
1356 * Each MSVW/SMVW controls a group of 4 eSPI virtual wires.
1357 * Host index located in b[7:0]
1358 * Reset source located in b[9:8]
1359 * Reset VW values SRC[3:0] located in b[15:12].
1360 * MSVW current VW state values located in bits[64, 72, 80, 88]
1361 * SMVW current VW state values located in bits[32, 40, 48, 56]
1362 */
xec_vw_cfg_properties(const struct xec_signal * p,uint32_t regaddr,uint8_t dir)1363 static void xec_vw_cfg_properties(const struct xec_signal *p, uint32_t regaddr, uint8_t dir)
1364 {
1365 uint32_t src_ofs = 4u;
1366 uint8_t src_pos = (8u * p->bit);
1367 uint8_t rst_state = (p->flags >> MCHP_DT_ESPI_VW_FLAG_RST_STATE_POS)
1368 & MCHP_DT_ESPI_VW_FLAG_RST_STATE_MSK0;
1369 uint8_t rst_src = rst_src = (p->flags >> MCHP_DT_ESPI_VW_FLAG_RST_SRC_POS)
1370 & MCHP_DT_ESPI_VW_FLAG_RST_SRC_MSK0;
1371
1372 if (dir) {
1373 src_ofs = 8u;
1374 }
1375
1376 if (rst_state || rst_src) { /* change reset source or state ? */
1377 sys_write8(0, regaddr); /* disable register */
1378
1379 uint8_t temp = sys_read8(regaddr + 1u);
1380
1381 if (rst_state) { /* change reset state and default value of this vwire? */
1382 rst_state--;
1383 if (rst_state) {
1384 temp |= BIT(p->bit + 4u);
1385 sys_set_bit(regaddr + src_ofs, src_pos);
1386 } else {
1387 temp |= ~BIT(p->bit + 4u);
1388 sys_clear_bit(regaddr + src_ofs, src_pos);
1389 }
1390 }
1391
1392 if (rst_src) { /* change reset source of all vwires in this group? */
1393 rst_src--;
1394 temp = (temp & ~0x3u) | (rst_src & 0x3u);
1395 }
1396
1397 sys_write8(temp, regaddr + 1u);
1398 }
1399
1400 if (sys_read8(regaddr) != p->host_idx) {
1401 sys_write8(p->host_idx, regaddr);
1402 }
1403 }
1404
1405 /* Check each VW register set host index is present.
1406 * Some VW's power up with the host index and others do not.
1407 * NOTE: Virtual wires are in groups of 4. Disabling one wire in a group
1408 * will disable all wires in the group. We do not implement disabling.
1409 */
xec_vw_config(const struct device * dev)1410 static void xec_vw_config(const struct device *dev)
1411 {
1412 for (int i = ESPI_VWIRE_SIGNAL_SLV_GPIO_0; i < ARRAY_SIZE(vw_tbl); i++) {
1413 const struct xec_signal *p = &vw_tbl[i];
1414 uint32_t regaddr = xec_smvw_addr(dev, p->xec_reg_idx);
1415 uint8_t dir = (p->flags >> MCHP_DT_ESPI_VW_FLAG_DIR_POS) & BIT(0);
1416 uint8_t en = (p->flags & BIT(MCHP_DT_ESPI_VW_FLAG_STATUS_POS));
1417
1418 if (dir) {
1419 regaddr = xec_msvw_addr(dev, p->xec_reg_idx);
1420 }
1421
1422 if (en) {
1423 xec_vw_cfg_properties(p, regaddr, dir);
1424 }
1425 }
1426 }
1427
xec_register_vw_handlers(const struct device * dev)1428 static int xec_register_vw_handlers(const struct device *dev)
1429 {
1430 for (int i = 0; i < ARRAY_SIZE(m2s_vwires_isr); i++) {
1431 const struct espi_vw_isr *vwi = &m2s_vwires_isr[i];
1432 struct xec_signal signal_info = vw_tbl[vwi->signal];
1433 uint8_t xec_id = signal_info.xec_reg_idx;
1434
1435 /* enables interrupt in eSPI MSVWn register */
1436 xec_espi_vw_intr_ctrl(dev, xec_id, signal_info.bit,
1437 MSVW_IRQ_SEL_EDGE_BOTH);
1438
1439 /* register handler */
1440 int ret = mchp_xec_ecia_set_callback(vwi->girq_id, vwi->girq_pos,
1441 vwi->the_isr, (void *)dev);
1442 if (ret) {
1443 return -EIO;
1444 }
1445
1446 mchp_xec_ecia_girq_src_en(vwi->girq_id, vwi->girq_pos);
1447 }
1448
1449 return 0;
1450 }
1451
1452 /*
1453 * Initialize eSPI hardware and associated peripherals blocks using eSPI
1454 * as their host interface.
1455 * We change VW capabilities reported to match the number of VWires the
1456 * driver is supporting.
1457 * A VW packet on the bus contains VW count followed by the VW groups.
1458 * The VW count is a zero based 6-bit value: (0 - 63) specifying the number of
1459 * groups in the packet.
1460 * A VW group consists of two bytes: VW host index and VW data. Each group
1461 * contains the state of 4 virtual wires.
1462 * The total supported virtual wires is 64 * 4 = 256.
1463 * MEC172x supports 11 MSVW groups and 11 SMVW groups.
1464 * NOTE: While ESPI_nRESET is active most of the eSPI hardware is held
1465 * in reset state.
1466 */
espi_xec_init(const struct device * dev)1467 static int espi_xec_init(const struct device *dev)
1468 {
1469 struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
1470 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev);
1471 struct espi_xec_data *const data = ESPI_XEC_DATA(dev);
1472 struct pcr_regs *pcr = XEC_PCR_REG_BASE;
1473 int ret;
1474
1475 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
1476 if (ret != 0) {
1477 LOG_ERR("XEC eSPI V2 pinctrl setup failed (%d)", ret);
1478 return ret;
1479 }
1480
1481 #ifdef ESPI_XEC_V2_DEBUG
1482 data->espi_rst_count = 0;
1483 #endif
1484 /* clear eSPI PCR sleep enable */
1485 z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_bitpos, 0);
1486
1487 /* Configure eSPI_PLTRST# to cause nSIO_RESET reset
1488 * NOTE: this is also clearing bit 0(PWR_INV) causing the internal
1489 * RESET_VCC to de-assert. Host facing peripherals will no longer
1490 * be held in reset.
1491 */
1492 pcr->PWR_RST_CTRL = MCHP_PCR_PR_CTRL_USE_ESPI_PLTRST;
1493 regs->PLTSRC = MCHP_ESPI_PLTRST_SRC_IS_VW;
1494
1495 /* Configure the channels and its capabilities based on build config */
1496 regs->CAP0 |= MCHP_ESPI_GBL_CAP0_VW_SUPP | MCHP_ESPI_GBL_CAP0_PC_SUPP;
1497
1498 regs->CAPVW = MAX(ESPI_NUM_MSVW, ESPI_NUM_SMVW);
1499 regs->CAPPC |= MCHP_ESPI_PC_CAP_MAX_PLD_SZ_64;
1500
1501 #ifdef CONFIG_ESPI_OOB_CHANNEL
1502 regs->CAP0 |= MCHP_ESPI_GBL_CAP0_OOB_SUPP;
1503 regs->CAPOOB |= MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_73;
1504
1505 k_sem_init(&data->tx_lock, 0, 1);
1506 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
1507 k_sem_init(&data->rx_lock, 0, 1);
1508 #endif /* CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC */
1509 #else
1510 regs->CAP0 &= ~MCHP_ESPI_GBL_CAP0_OOB_SUPP;
1511 #endif
1512
1513 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1514 regs->CAP0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP |
1515 MCHP_ESPI_FC_CAP_MAX_PLD_SZ_64;
1516 regs->CAPFC |= MCHP_ESPI_FC_CAP_SHARE_MAF_SAF |
1517 MCHP_ESPI_FC_CAP_MAX_RD_SZ_64;
1518
1519 k_sem_init(&data->flash_lock, 0, 1);
1520 #else
1521 regs->CAP0 &= ~MCHP_ESPI_GBL_CAP0_FC_SUPP;
1522 #endif
1523
1524 /* Clear reset interrupt status and enable interrupts */
1525 regs->ERIS = MCHP_ESPI_RST_ISTS;
1526 regs->ERIE |= MCHP_ESPI_RST_IEN;
1527 regs->PCSTS = MCHP_ESPI_PC_STS_EN_CHG;
1528 regs->PCIEN |= MCHP_ESPI_PC_IEN_EN_CHG;
1529
1530 xec_vw_config(dev);
1531
1532 /* register VWire handlers with their aggregated GIRQs
1533 * in the ECIA driver
1534 */
1535 ret = xec_register_vw_handlers(dev);
1536 if (ret) {
1537 LOG_ERR("XEX eSPI V2 register VW handlers error %d", ret);
1538 return ret;
1539 }
1540
1541 /* Enable interrupts for each logical channel enable assertion */
1542 xec_espi_bus_intr_ctl(dev, pc_girq_idx, 1);
1543 xec_espi_bus_intr_ctl(dev, vw_ch_en_girq_idx, 1);
1544 xec_espi_bus_intr_ctl(dev, rst_girq_idx, 1);
1545
1546 #ifdef CONFIG_ESPI_OOB_CHANNEL
1547 espi_init_oob(dev);
1548 #endif
1549 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1550 espi_init_flash(dev);
1551 #endif
1552
1553 espi_xec_connect_irqs(dev);
1554
1555 ret = xec_host_dev_connect_irqs(dev);
1556
1557 return ret;
1558 }
1559
