1 /*
2 *
3 * Copyright (c) 2017 Linaro Limited.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8
9 #include <soc.h>
10 #include <stm32_ll_bus.h>
11 #include <stm32_ll_rcc.h>
12 #include <stm32_ll_utils.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
16 #include "clock_stm32_ll_common.h"
17
18 #if defined(STM32_PLL_ENABLED)
19
20 /**
21 * @brief Return PLL source
22 */
23 __unused
get_pll_source(void)24 static uint32_t get_pll_source(void)
25 {
26 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
27 return LL_RCC_PLLSOURCE_HSI;
28 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
29 return LL_RCC_PLLSOURCE_HSE;
30 }
31
32 __ASSERT(0, "Invalid source");
33 return 0;
34 }
35
36 /**
37 * @brief get the pll source frequency
38 */
39 __unused
get_pllsrc_frequency(void)40 uint32_t get_pllsrc_frequency(void)
41 {
42 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
43 return STM32_HSI_FREQ;
44 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
45 return STM32_HSE_FREQ;
46 }
47
48 __ASSERT(0, "Invalid source");
49 return 0;
50 }
51
52 /**
53 * @brief Set up pll configuration
54 */
55 __unused
config_pll_sysclock(void)56 void config_pll_sysclock(void)
57 {
58 LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
59 pllm(STM32_PLL_M_DIVISOR),
60 STM32_PLL_N_MULTIPLIER,
61 pllp(STM32_PLL_P_DIVISOR));
62 }
63
64 #endif /* defined(STM32_PLL_ENABLED) */
65
66 #ifdef STM32_PLLI2S_ENABLED
67
68 /**
69 * @brief Set up PLL I2S configuration
70 */
71 __unused
config_plli2s(void)72 void config_plli2s(void)
73 {
74 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_plli2s_clock)
75 LL_RCC_PLLI2S_ConfigDomain_I2S(get_pll_source(),
76 pllm(STM32_PLLI2S_M_DIVISOR),
77 STM32_PLLI2S_N_MULTIPLIER,
78 plli2sr(STM32_PLLI2S_R_DIVISOR));
79 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f412_plli2s_clock)
80 LL_RCC_PLL_ConfigDomain_I2S(get_pll_source(),
81 plli2sm(STM32_PLLI2S_M_DIVISOR),
82 STM32_PLLI2S_N_MULTIPLIER,
83 plli2sr(STM32_PLLI2S_R_DIVISOR));
84 #endif
85 }
86
87 #endif /* STM32_PLLI2S_ENABLED */
88
89 /**
90 * @brief Activate default clocks
91 */
config_enable_default_clocks(void)92 void config_enable_default_clocks(void)
93 {
94 /* Power Interface clock enabled by default */
95 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
96 }
97
