1 /*
2 *
3 * Copyright (c) 2017 Linaro Limited.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8
9 #include <soc.h>
10 #include <stm32_ll_bus.h>
11 #include <stm32_ll_rcc.h>
12 #include <stm32_ll_utils.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
16 #include "clock_stm32_ll_common.h"
17
18 #if defined(STM32_PLL_ENABLED)
19
20 /**
21 * @brief Set up pll configuration
22 */
23 __unused
config_pll_sysclock(void)24 void config_pll_sysclock(void)
25 {
26 uint32_t pll_source, pll_mul, pll_div;
27
28 /*
29 * PLL MUL
30 * 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
31 * 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
32 * 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
33 * ...
34 * 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
35 */
36 pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos);
37
38 /*
39 * PLL PREDIV
40 * 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
41 * 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
42 * 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
43 * ...
44 * 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
45 */
46 pll_div = STM32_PLL_PREDIV - 1;
47
48 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
49 /*
50 * PREDIV1 support is a specific RCC configuration present on
51 * following SoCs: STM32F04xx, STM32F07xx, STM32F09xx,
52 * STM32F030xC, STM32F302xE, STM32F303xE and STM32F39xx
53 * cf Reference manual for more details
54 */
55
56 /* Configure PLL source */
57 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
58 pll_source = LL_RCC_PLLSOURCE_HSE;
59 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
60 pll_source = LL_RCC_PLLSOURCE_HSI;
61 } else {
62 __ASSERT(0, "Invalid source");
63 }
64
65 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul, pll_div);
66 #else
67 /* Configure PLL source */
68 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
69 pll_source = LL_RCC_PLLSOURCE_HSE | pll_div;
70 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
71 pll_source = LL_RCC_PLLSOURCE_HSI_DIV_2;
72 } else {
73 __ASSERT(0, "Invalid source");
74 }
75
76 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul);
77 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
78 }
79
80 /**
81 * @brief Return pllout frequency
82 */
83 __unused
get_pllout_frequency(void)84 uint32_t get_pllout_frequency(void)
85 {
86 uint32_t pll_input_freq, pll_mul, pll_div;
87
88 /*
89 * PLL MUL
90 * 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
91 * 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
92 * 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
93 * ...
94 * 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
95 */
96 pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos);
97
98 /*
99 * PLL PREDIV
100 * 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
101 * 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
102 * 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
103 * ...
104 * 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
105 */
106 pll_div = STM32_PLL_PREDIV - 1;
107
108 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
109 /*
110 * PREDIV1 support is a specific RCC configuration present on
111 * following SoCs: STM32F04xx, STM32F07xx, STM32F09xx,
112 * STM32F030xC, STM32F302xE, STM32F303xE and STM32F39xx
113 * cf Reference manual for more details
114 */
115
116 /* Configure PLL source */
117 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
118 pll_input_freq = STM32_HSE_FREQ;
119 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
120 pll_input_freq = STM32_HSI_FREQ;
121 } else {
122 return 0;
123 }
124
125 return __LL_RCC_CALC_PLLCLK_FREQ(pll_input_freq, pll_mul, pll_div);
126 #else
127 /* Configure PLL source */
128 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
129 pll_input_freq = STM32_HSE_FREQ;
130 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
131 pll_input_freq = STM32_HSI_FREQ / 2;
132 } else {
133 return 0;
134 }
135
136 return __LL_RCC_CALC_PLLCLK_FREQ(pll_input_freq, pll_mul);
137 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
138 }
139
140 #endif /* defined(STM32_PLL_ENABLED) */
141
142 /**
143 * @brief Activate default clocks
144 */
config_enable_default_clocks(void)145 void config_enable_default_clocks(void)
146 {
147 /* Enable PWR clock, required to access BDCR and PWR_CR */
148 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
149
150 #ifndef CONFIG_SOC_SERIES_STM32F3X
151 #if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32)
152 /* Enable System Configuration Controller clock. */
153 LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
154 #endif
155 #else
156 #if defined(CONFIG_USB_DC_STM32) && defined(SYSCFG_CFGR1_USB_IT_RMP)
157 /* Enable System Configuration Controller clock. */
158 /* SYSCFG is required to remap IRQ to avoid conflicts with CAN */
159 /* cf §14.1.3, RM0316 */
160 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
161 #endif
162 #endif /* !CONFIG_SOC_SERIES_STM32F3X */
163 }
164
