1 /*
2 * Copyright (c) 2021 Google Inc
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_bbram
8
9 #include <errno.h>
10
11 #include <zephyr/drivers/bbram.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/sys/util.h>
14
15 #include <chip_chipregs.h>
16
17 LOG_MODULE_REGISTER(bbram, CONFIG_BBRAM_LOG_LEVEL);
18
19 #define BRAM_VALID_MAGIC 0x4252414D /* "BRAM" */
20 #define BRAM_VALID_MAGIC_FIELD0 (BRAM_VALID_MAGIC & 0xff)
21 #define BRAM_VALID_MAGIC_FIELD1 ((BRAM_VALID_MAGIC >> 8) & 0xff)
22 #define BRAM_VALID_MAGIC_FIELD2 ((BRAM_VALID_MAGIC >> 16) & 0xff)
23 #define BRAM_VALID_MAGIC_FIELD3 ((BRAM_VALID_MAGIC >> 24) & 0xff)
24
25 /** Device config */
26 struct bbram_it8xxx2_config {
27 /** BBRAM base address */
28 uintptr_t base_addr;
29 /** BBRAM size (Unit:bytes) */
30 int size;
31 };
32
bbram_it8xxx2_read(const struct device * dev,size_t offset,size_t size,uint8_t * data)33 static int bbram_it8xxx2_read(const struct device *dev, size_t offset, size_t size, uint8_t *data)
34 {
35 const struct bbram_it8xxx2_config *config = dev->config;
36
37 if (size < 1 || offset + size > config->size) {
38 return -EFAULT;
39 }
40
41 bytecpy(data, ((uint8_t *)config->base_addr + offset), size);
42 return 0;
43 }
44
bbram_it8xxx2_write(const struct device * dev,size_t offset,size_t size,const uint8_t * data)45 static int bbram_it8xxx2_write(const struct device *dev, size_t offset, size_t size,
46 const uint8_t *data)
47 {
48 const struct bbram_it8xxx2_config *config = dev->config;
49
50 if (size < 1 || offset + size > config->size) {
51 return -EFAULT;
52 }
53
54 bytecpy(((uint8_t *)config->base_addr + offset), data, size);
55 return 0;
56 }
57
58 static const struct bbram_driver_api bbram_it8xxx2_driver_api = {
59 .read = bbram_it8xxx2_read,
60 .write = bbram_it8xxx2_write,
61 };
62
bbram_it8xxx2_init(const struct device * dev)63 static int bbram_it8xxx2_init(const struct device *dev)
64 {
65 const struct bbram_it8xxx2_config *config = dev->config;
66 uint8_t *base_addr = (uint8_t *)config->base_addr;
67 uint8_t *bram_valid_flag0 = base_addr + BRAM_IDX_VALID_FLAGS0;
68 uint8_t *bram_valid_flag1 = base_addr + BRAM_IDX_VALID_FLAGS1;
69 uint8_t *bram_valid_flag2 = base_addr + BRAM_IDX_VALID_FLAGS2;
70 uint8_t *bram_valid_flag3 = base_addr + BRAM_IDX_VALID_FLAGS3;
71
72 if ((*bram_valid_flag0 != BRAM_VALID_MAGIC_FIELD0) ||
73 (*bram_valid_flag1 != BRAM_VALID_MAGIC_FIELD1) ||
74 (*bram_valid_flag2 != BRAM_VALID_MAGIC_FIELD2) ||
75 (*bram_valid_flag3 != BRAM_VALID_MAGIC_FIELD3)) {
76 /*
77 * Magic does not match, so BRAM must be uninitialized. Clear
78 * entire Bank0 BRAM, and set magic value.
79 */
80 for (int i = 0; i < BRAM_IDX_VALID_FLAGS0; i++) {
81 *(base_addr + i) = 0;
82 }
83
84 *bram_valid_flag0 = BRAM_VALID_MAGIC_FIELD0;
85 *bram_valid_flag1 = BRAM_VALID_MAGIC_FIELD1;
86 *bram_valid_flag2 = BRAM_VALID_MAGIC_FIELD2;
87 *bram_valid_flag3 = BRAM_VALID_MAGIC_FIELD3;
88 }
89
90 return 0;
91 }
92
93 #define BBRAM_INIT(inst) \
94 static const struct bbram_it8xxx2_config bbram_cfg_##inst = { \
95 .base_addr = DT_INST_REG_ADDR(inst), \
96 .size = DT_INST_REG_SIZE(inst), \
97 }; \
98 DEVICE_DT_INST_DEFINE(inst, bbram_it8xxx2_init, NULL, NULL, &bbram_cfg_##inst, \
99 PRE_KERNEL_1, CONFIG_BBRAM_INIT_PRIORITY, \
100 &bbram_it8xxx2_driver_api);
101
102 DT_INST_FOREACH_STATUS_OKAY(BBRAM_INIT);
103
