1 /*
2 * Copyright (c) 2021 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_adc
8
9 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
10 #include <zephyr/logging/log.h>
11 LOG_MODULE_REGISTER(adc_ite_it8xxx2);
12
13 #include <zephyr/drivers/adc.h>
14 #include <zephyr/drivers/pinctrl.h>
15 #include <soc.h>
16 #include <soc_dt.h>
17 #include <errno.h>
18 #include <assert.h>
19 #include <zephyr/irq.h>
20
21 #define ADC_CONTEXT_USES_KERNEL_TIMER
22 #include "adc_context.h"
23
24 /* ADC internal reference voltage (Unit:mV) */
25 #ifdef CONFIG_ADC_IT8XXX2_VOL_FULL_SCALE
26 #define IT8XXX2_ADC_VREF_VOL 3300
27 #else
28 #define IT8XXX2_ADC_VREF_VOL 3000
29 #endif
30 /* ADC channels disabled */
31 #define IT8XXX2_ADC_CHANNEL_DISABLED 0x1F
32 /* ADC sample time delay (Unit:us) */
33 #define IT8XXX2_ADC_SAMPLE_TIME_US 500
34 /* Wait next clock rising (Clock source 32.768K) */
35 #define IT8XXX2_WAIT_NEXT_CLOCK_TIME_US 31
36 /* ADC channels offset */
37 #define ADC_CHANNEL_SHIFT 5
38 #define ADC_CHANNEL_OFFSET(ch) ((ch)-CHIP_ADC_CH13-ADC_CHANNEL_SHIFT)
39
40 #ifdef CONFIG_ADC_IT8XXX2_VOL_FULL_SCALE
41 #define ADC_0_7_FULL_SCALE_MASK GENMASK(7, 0)
42 #define ADC_8_10_FULL_SCALE_MASK GENMASK(2, 0)
43 #define ADC_13_16_FULL_SCALE_MASK GENMASK(3, 0)
44 #endif
45
46 /* List of ADC channels. */
47 enum chip_adc_channel {
48 CHIP_ADC_CH0 = 0,
49 CHIP_ADC_CH1,
50 CHIP_ADC_CH2,
51 CHIP_ADC_CH3,
52 CHIP_ADC_CH4,
53 CHIP_ADC_CH5,
54 CHIP_ADC_CH6,
55 CHIP_ADC_CH7,
56 CHIP_ADC_CH13,
57 CHIP_ADC_CH14,
58 CHIP_ADC_CH15,
59 CHIP_ADC_CH16,
60 CHIP_ADC_COUNT,
61 };
62
63 struct adc_it8xxx2_data {
64 struct adc_context ctx;
65 struct k_sem sem;
66 /* Channel ID */
67 uint32_t ch;
68 /* Save ADC result to the buffer. */
69 uint16_t *buffer;
70 /*
71 * The sample buffer pointer should be prepared
72 * for writing of next sampling results.
73 */
74 uint16_t *repeat_buffer;
75 };
76
77 /*
78 * Structure adc_it8xxx2_cfg is about the setting of adc
79 * this config will be used at initial time
80 */
81 struct adc_it8xxx2_cfg {
82 /* ADC alternate configuration */
83 const struct pinctrl_dev_config *pcfg;
84 };
85
86 #define ADC_IT8XXX2_REG_BASE \
87 ((struct adc_it8xxx2_regs *)(DT_INST_REG_ADDR(0)))
88
adc_it8xxx2_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)89 static int adc_it8xxx2_channel_setup(const struct device *dev,
90 const struct adc_channel_cfg *channel_cfg)
91 {
92 uint8_t channel_id = channel_cfg->channel_id;
93
94 if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
95 LOG_ERR("Selected ADC acquisition time is not valid");
96 return -EINVAL;
97 }
98
99 /* Support channels 0~7 and 13~16 */
100 if (!((channel_id >= 0 && channel_id <= 7) ||
101 (channel_id >= 13 && channel_id <= 16))) {
102 LOG_ERR("Channel %d is not valid", channel_id);
103 return -EINVAL;
104 }
105
106 /* Channels 13~16 should be shifted by 5 */
107 if (channel_id > CHIP_ADC_CH7) {
108 channel_id -= ADC_CHANNEL_SHIFT;
109 }
110
111 if (channel_cfg->gain != ADC_GAIN_1) {
112 LOG_ERR("Invalid channel gain");
113 return -EINVAL;
114 }
115
116 if (channel_cfg->reference != ADC_REF_INTERNAL) {
117 LOG_ERR("Invalid channel reference");
118 return -EINVAL;
119 }
120
121 LOG_DBG("Channel setup succeeded!");
122 return 0;
123 }
124
adc_disable_measurement(uint32_t ch)125 static void adc_disable_measurement(uint32_t ch)
126 {
127 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
128
129 if (ch <= CHIP_ADC_CH7) {
130 /*
131 * Disable measurement.
132 * bit(4:0) = 0x1f : channel disable
133 */
134 adc_regs->VCH0CTL = IT8XXX2_ADC_DATVAL |
135 IT8XXX2_ADC_CHANNEL_DISABLED;
136 } else {
137 /*
138 * Channels 13~16 controller setting.
139 * bit7 = 1: End of conversion. New data is available in
140 * VCHDATL/VCHDATM.
141 */
142 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(ch)].VCHCTL =
143 IT8XXX2_ADC_DATVAL;
144 }
145
146 /* ADC module disable */
147 adc_regs->ADCCFG &= ~IT8XXX2_ADC_ADCEN;
148
149 /* disable adc interrupt */
150 irq_disable(DT_INST_IRQN(0));
151 }
152
adc_data_valid(const struct device * dev)153 static int adc_data_valid(const struct device *dev)
154 {
155 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
156 struct adc_it8xxx2_data *data = dev->data;
157
158 return (data->ch <= CHIP_ADC_CH7) ?
159 (adc_regs->VCH0CTL & IT8XXX2_ADC_DATVAL) :
160 (adc_regs->ADCDVSTS2 & BIT(ADC_CHANNEL_OFFSET(data->ch)));
161 }
162
163 /* Get result for each ADC selected channel. */
adc_it8xxx2_get_sample(const struct device * dev)164 static void adc_it8xxx2_get_sample(const struct device *dev)
165 {
166 struct adc_it8xxx2_data *data = dev->data;
167 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
168
169 if (adc_data_valid(dev)) {
170 if (data->ch <= CHIP_ADC_CH7) {
171 /* Read adc raw data of msb and lsb */
172 *data->buffer++ = adc_regs->VCH0DATM << 8 |
173 adc_regs->VCH0DATL;
174 } else {
175 /* Read adc channels 13~16 raw data of msb and lsb */
176 *data->buffer++ =
177 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(data->ch)].VCHDATM << 8 |
178 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(data->ch)].VCHDATL;
179 }
180 } else {
181 LOG_WRN("ADC failed to read (regs=%x, ch=%d)",
182 adc_regs->ADCDVSTS, data->ch);
183 }
184
185 adc_disable_measurement(data->ch);
186 }
187
adc_poll_valid_data(void)188 static void adc_poll_valid_data(void)
189 {
190 const struct device *const dev = DEVICE_DT_INST_GET(0);
191 int valid = 0;
192
193 /*
194 * If the polling waits for a valid data longer than
195 * the sampling time limit, the program will return.
196 */
197 for (int i = 0U; i < (IT8XXX2_ADC_SAMPLE_TIME_US /
198 IT8XXX2_WAIT_NEXT_CLOCK_TIME_US); i++) {
199 /* Wait next clock time (1/32.768K~=30.5us) */
200 k_busy_wait(IT8XXX2_WAIT_NEXT_CLOCK_TIME_US);
201
202 if (adc_data_valid(dev)) {
203 valid = 1;
204 break;
205 }
206 }
207
208 if (valid) {
209 adc_it8xxx2_get_sample(dev);
210 } else {
211 LOG_ERR("Sampling timeout.");
212 return;
213 }
214 }
215
adc_enable_measurement(uint32_t ch)216 static void adc_enable_measurement(uint32_t ch)
217 {
218 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
219 const struct device *const dev = DEVICE_DT_INST_GET(0);
220 struct adc_it8xxx2_data *data = dev->data;
221
222 if (ch <= CHIP_ADC_CH7) {
223 /* Select and enable a voltage channel input for measurement */
224 adc_regs->VCH0CTL = (IT8XXX2_ADC_DATVAL | IT8XXX2_ADC_INTDVEN) + ch;
225 } else {
226 /* Channels 13~16 controller setting */
227 adc_regs->adc_vchs_ctrl[ADC_CHANNEL_OFFSET(ch)].VCHCTL =
228 IT8XXX2_ADC_DATVAL | IT8XXX2_ADC_INTDVEN | IT8XXX2_ADC_VCHEN;
229 }
230
231 /* ADC module enable */
232 adc_regs->ADCCFG |= IT8XXX2_ADC_ADCEN;
233
234 /*
235 * In the sampling process, it is possible to read multiple channels
236 * at a time. The ADC sampling of it8xxx2 needs to read each channel
237 * in sequence, so it needs to wait for an interrupt to read data in
238 * the loop through k_sem_take(). But k_timer_start() is used in the
239 * interval test in test_adc.c, so we need to use polling wait instead
240 * of k_sem_take() to wait, otherwise it will cause kernel panic.
241 *
242 * k_is_in_isr() can determine whether to use polling or k_sem_take()
243 * at present.
244 */
245 if (k_is_in_isr()) {
246 /* polling wait for a valid data */
247 adc_poll_valid_data();
248 } else {
249 /* Enable adc interrupt */
250 irq_enable(DT_INST_IRQN(0));
251 /* Wait for an interrupt to read valid data. */
252 k_sem_take(&data->sem, K_FOREVER);
253 }
254 }
255
check_buffer_size(const struct adc_sequence * sequence,uint8_t active_channels)256 static int check_buffer_size(const struct adc_sequence *sequence,
257 uint8_t active_channels)
258 {
259 size_t needed_buffer_size;
260
261 needed_buffer_size = active_channels * sizeof(uint16_t);
262 if (sequence->options) {
263 needed_buffer_size *= (1 + sequence->options->extra_samplings);
264 }
265
266 if (sequence->buffer_size < needed_buffer_size) {
267 LOG_ERR("Provided buffer is too small (%u/%u)",
268 sequence->buffer_size, needed_buffer_size);
269 return -ENOMEM;
270 }
271
272 return 0;
273 }
274
adc_it8xxx2_start_read(const struct device * dev,const struct adc_sequence * sequence)275 static int adc_it8xxx2_start_read(const struct device *dev,
276 const struct adc_sequence *sequence)
277 {
278 struct adc_it8xxx2_data *data = dev->data;
279 uint32_t channel_mask = sequence->channels;
280
281 /* Channels 13~16 should be shifted to the right by 5 */
282 if (channel_mask > BIT(CHIP_ADC_CH7)) {
283 channel_mask >>= ADC_CHANNEL_SHIFT;
284 }
285
286 if (!channel_mask || channel_mask & ~BIT_MASK(CHIP_ADC_COUNT)) {
287 LOG_ERR("Invalid selection of channels");
288 return -EINVAL;
289 }
290
291 if (!sequence->resolution) {
292 LOG_ERR("ADC resolution is not valid");
293 return -EINVAL;
294 }
295 LOG_DBG("Configure resolution=%d", sequence->resolution);
296
297 data->buffer = sequence->buffer;
298
299 adc_context_start_read(&data->ctx, sequence);
300
301 return adc_context_wait_for_completion(&data->ctx);
302 }
303
adc_context_start_sampling(struct adc_context * ctx)304 static void adc_context_start_sampling(struct adc_context *ctx)
305 {
306 struct adc_it8xxx2_data *data =
307 CONTAINER_OF(ctx, struct adc_it8xxx2_data, ctx);
308 uint32_t channels = ctx->sequence.channels;
309 uint8_t channel_count = 0;
310
311 data->repeat_buffer = data->buffer;
312
313 /*
314 * The ADC sampling of it8xxx2 needs to read each channel
315 * in sequence.
316 */
317 while (channels) {
318 data->ch = find_lsb_set(channels) - 1;
319 channels &= ~BIT(data->ch);
320
321 adc_enable_measurement(data->ch);
322
323 channel_count++;
324 }
325
326 if (check_buffer_size(&ctx->sequence, channel_count)) {
327 return;
328 }
329
330 adc_context_on_sampling_done(&data->ctx, DEVICE_DT_INST_GET(0));
331 }
332
adc_it8xxx2_read(const struct device * dev,const struct adc_sequence * sequence)333 static int adc_it8xxx2_read(const struct device *dev,
334 const struct adc_sequence *sequence)
335 {
336 struct adc_it8xxx2_data *data = dev->data;
337 int err;
338
339 adc_context_lock(&data->ctx, false, NULL);
340 err = adc_it8xxx2_start_read(dev, sequence);
341 adc_context_release(&data->ctx, err);
342
343 return err;
344 }
345
346 #ifdef CONFIG_ADC_ASYNC
adc_it8xxx2_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)347 static int adc_it8xxx2_read_async(const struct device *dev,
348 const struct adc_sequence *sequence,
349 struct k_poll_signal *async)
350 {
351 struct adc_it8xxx2_data *data = dev->data;
352 int err;
353
354 adc_context_lock(&data->ctx, true, async);
355 err = adc_it8xxx2_start_read(dev, sequence);
356 adc_context_release(&data->ctx, err);
357
358 return err;
359 }
360 #endif /* CONFIG_ADC_ASYNC */
361
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)362 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
363 bool repeat_sampling)
364 {
365 struct adc_it8xxx2_data *data =
366 CONTAINER_OF(ctx, struct adc_it8xxx2_data, ctx);
367
368 if (repeat_sampling) {
369 data->buffer = data->repeat_buffer;
370 }
371 }
372
adc_it8xxx2_isr(const struct device * dev)373 static void adc_it8xxx2_isr(const struct device *dev)
374 {
375 struct adc_it8xxx2_data *data = dev->data;
376
377 LOG_DBG("ADC ISR triggered.");
378
379 adc_it8xxx2_get_sample(dev);
380
381 k_sem_give(&data->sem);
382 }
383
384 static const struct adc_driver_api api_it8xxx2_driver_api = {
385 .channel_setup = adc_it8xxx2_channel_setup,
386 .read = adc_it8xxx2_read,
387 #ifdef CONFIG_ADC_ASYNC
388 .read_async = adc_it8xxx2_read_async,
389 #endif
390 .ref_internal = IT8XXX2_ADC_VREF_VOL,
391 };
392
393 /*
394 * ADC analog accuracy initialization (only once after VSTBY power on)
395 *
396 * Write 1 to this bit and write 0 to this bit immediately once and
397 * only once during the firmware initialization and do not write 1 again
398 * after initialization since IT83xx takes much power consumption
399 * if this bit is set as 1
400 */
adc_accuracy_initialization(void)401 static void adc_accuracy_initialization(void)
402 {
403 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
404
405 /* Start adc accuracy initialization */
406 adc_regs->ADCSTS |= IT8XXX2_ADC_AINITB;
407 /* Enable automatic HW calibration. */
408 adc_regs->KDCTL |= IT8XXX2_ADC_AHCE;
409 /* Stop adc accuracy initialization */
410 adc_regs->ADCSTS &= ~IT8XXX2_ADC_AINITB;
411 }
412
adc_it8xxx2_init(const struct device * dev)413 static int adc_it8xxx2_init(const struct device *dev)
414 {
415 const struct adc_it8xxx2_cfg *config = dev->config;
416 struct adc_it8xxx2_data *data = dev->data;
417 struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
418 int status;
419
420 #ifdef CONFIG_ADC_IT8XXX2_VOL_FULL_SCALE
421 /* ADC input voltage 0V ~ AVCC (3.3V) is mapped into 0h-3FFh */
422 adc_regs->ADCIVMFSCS1 = ADC_0_7_FULL_SCALE_MASK;
423 adc_regs->ADCIVMFSCS2 = ADC_8_10_FULL_SCALE_MASK;
424 adc_regs->ADCIVMFSCS3 = ADC_13_16_FULL_SCALE_MASK;
425 #endif
426 /* ADC analog accuracy initialization */
427 adc_accuracy_initialization();
428
429 /* Set the pin to ADC alternate function. */
430 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
431 if (status < 0) {
432 LOG_ERR("Failed to configure ADC pins");
433 return status;
434 }
435
436 /*
437 * The ADC channel conversion time is 30.8*(SCLKDIV+1) us.
438 * (Current setting is 61.6us)
439 *
440 * NOTE: A sample time delay (60us) also need to be included in
441 * conversion time.
442 * In addition, the ADC has a waiting time of 202.8us for
443 * voltage stabilization.
444 *
445 * So the final ADC sample time result is ~= 324.4us.
446 */
447 adc_regs->ADCSTS &= ~IT8XXX2_ADC_ADCCTS1;
448 adc_regs->ADCCFG &= ~IT8XXX2_ADC_ADCCTS0;
449 /*
450 * bit[5-0]@ADCCTL : SCLKDIV
451 * SCLKDIV has to be equal to or greater than 1h;
452 */
453 adc_regs->ADCCTL = 1;
454 /*
455 * Enable this bit, and data of VCHxDATL/VCHxDATM will be
456 * kept until data valid is cleared.
457 */
458 adc_regs->ADCGCR |= IT8XXX2_ADC_DBKEN;
459
460 IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
461 adc_it8xxx2_isr, DEVICE_DT_INST_GET(0), 0);
462
463 k_sem_init(&data->sem, 0, 1);
464 adc_context_unlock_unconditionally(&data->ctx);
465
466 return 0;
467 }
468
469 static struct adc_it8xxx2_data adc_it8xxx2_data_0 = {
470 ADC_CONTEXT_INIT_TIMER(adc_it8xxx2_data_0, ctx),
471 ADC_CONTEXT_INIT_LOCK(adc_it8xxx2_data_0, ctx),
472 ADC_CONTEXT_INIT_SYNC(adc_it8xxx2_data_0, ctx),
473 };
474
475 PINCTRL_DT_INST_DEFINE(0);
476
477 static const struct adc_it8xxx2_cfg adc_it8xxx2_cfg_0 = {
478 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
479 };
480
481 DEVICE_DT_INST_DEFINE(0, adc_it8xxx2_init,
482 NULL,
483 &adc_it8xxx2_data_0,
484 &adc_it8xxx2_cfg_0, PRE_KERNEL_1,
485 CONFIG_ADC_INIT_PRIORITY,
486 &api_it8xxx2_driver_api);
487
