1.. _edac_ibecc:
2
3In Band Error Correction Code (IBECC)
4#####################################
5
6Overview
7********
8
9The mechanism initially found in Intel Elkhart Lake SOCs and later boards is
10an integrated memory controller with IBECC.
11
12The In-Band Error Correction Code (IBECC) improves reliability by providing
13error detection and correction. IBECC can work for all or for specific regions
14of physical memory space. The IBECC is useful for memory technologies that do
15not support the out-of-band ECC.
16
17IBECC adds memory overhead of 1/32 of the memory. This memory is not accessible
18and used to store ECC syndrome data. IBECC converts read / write transactions
19to two separate transactions: one for actual data and another for cache line
20containing ECC value.
21
22There is a debug feature IBECC Error Injection which helps to debug and verify
23IBECC functionality. ECC errors are injected on the write path and cause ECC
24errors on the read path.
25
26IBECC Configuration
27*******************
28
29There are three IBECC operation modes which can be selected by Bootloader. They
30are listed below:
31
32* OPERATION_MODE = 0x0 sets functional mode to protect requests based on
33  address range
34
35* OPERATION_MODE = 0x1 sets functional mode to all requests not be protected and
36  to ignore range checks
37
38* OPERATION_MODE = 0x2 sets functional mode to protect all requests and ignore
39  range checks
40
41IBECC operational mode is configured through BIOS or Bootloader. For operation
42mode 0 there are more BIOS configuration options such as memory regions.
43
44Due to high security risk Error Injection capability should not be enabled for
45production. Error Injection is only enabled for tests.
46
47IBECC Logging
48*************
49
50IBECC logs the following fields:
51
52* Error Address
53
54* Error Syndrome
55
56* Error Type
57
58  * Correctable Error (CE) - error is detected and corrected by IBECC module.
59
60  * Uncorrectable Error (UE) - error is detected by IBECC module and not
61    automatically corrected.
62
63The IBECC driver provides error type for the higher-level application to
64implement desired policy with respect for handling those memory errors. Error
65syndrome is not used in the IBECC driver but provided to higher-level
66application.
67
68Usage notes
69***********
70
71Exceptional care needs to be taken with Non Maskable Interrupt (NMI). NMI will
72arrive at any time, even if the local CPU has disabled interrupts. That means
73that no locking mechanism can protect code against an NMI happening. Zephyr's
74IPC mechanisms universally use local IRQ locking as the base layer for all
75higher-level synchronization primitives. So, you cannot share anything that is
76"protected" by a lock with an NMI, because the protection does not work. The
77only tool you have available for synchronization in the Zephyr API that works
78against an NMI is the atomic layer. This also applies to callback function
79which is called by NMI handler.
80
81Configuration option
82********************
83
84Related configuration option:
85
86* :kconfig:option:`CONFIG_EDAC_IBECC`
87