1/*
2 * Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH
3 * Copyright (c) 2017 Linaro Limited
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/dts-v1/;
9#include <nordic/nrf52840_qiaa.dtsi>
10#include "reel_board.dtsi"
11#include "reel_board_v2-pinctrl.dtsi"
12
13/ {
14	model = "reel board v2";
15	compatible = "phytec,reel_board_v2";
16
17	chosen {
18		zephyr,console = &uart0;
19		zephyr,shell-uart = &uart0;
20		zephyr,uart-mcumgr = &uart0;
21		zephyr,bt-mon-uart = &uart0;
22		zephyr,bt-c2h-uart = &uart0;
23		zephyr,sram = &sram0;
24		zephyr,flash = &flash0;
25		zephyr,code-partition = &slot0_partition;
26		zephyr,display = &ssd16xx;
27	};
28
29	aliases {
30		watchdog0 = &wdt0;
31	};
32};
33
34&spi1 {
35	compatible = "nordic,nrf-spi";
36	status = "okay";
37	cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
38
39	pinctrl-0 = <&spi1_default>;
40	pinctrl-1 = <&spi1_sleep>;
41	pinctrl-names = "default", "sleep";
42	ssd16xx: ssd16xxfb@0 {
43		compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a";
44		spi-max-frequency = <4000000>;
45		reg = <0>;
46		width = <250>;
47		height = <122>;
48		reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
49		dc-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
50		busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
51
52		full {
53			gdv = [15];
54			sdv = [41 a8 32];
55			vcom = <0x26>;
56			border-waveform = <0x03>;
57			dummy-line = <0x30>;
58			gate-line-width = <0x0a>;
59			lut = [
60				/*
61				 * Waveform Composition
62				 *
63				 * There are 7 Voltage Source (VS) Level groups
64				 * n = {0,1,2...6}, each group contains
65				 * 4 phases x = {A,B,C,D}.
66				 * 2 bits represent the voltage in a phase:
67				 * 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2
68				 *
69				 * For example 0x80 represents sequence VSL-VSS-VSS-VSS,
70				 */
71				80 60 40 00 00 00 00 /* LUT0: BB: VS 0..6 */
72				10 60 20 00 00 00 00 /* LUT1: BW: VS 0..6 */
73				80 60 40 00 00 00 00 /* LUT2: WB: VS 0..6 */
74				10 60 20 00 00 00 00 /* LUT3: WW: VS 0..6 */
75				00 00 00 00 00 00 00 /* LUT4: VCOM: VS 0..6 */
76				/*
77				 * TPnx determines the length of each phase,
78				 * and RPn repeat count of a sequence.
79				 * TPnA, TPnB, TPnC, TPnD, RPn
80				 *
81				 * For example TP0A=3, TP0B=3, and RP0=2:
82				 * VS sequence                    : VSL-VSS-VSS-VSS
83				 * number of Gate Pulses (length) :  3   3   0   0
84				 * repeat count                   :        2
85				 */
86				03 03 00 00 02 /* TP0A TP0B TP0C TP0D RP0 */
87				09 09 00 00 02 /* TP1A TP1B TP1C TP1D RP1 */
88				03 03 00 00 02 /* TP2A TP2B TP2C TP2D RP2 */
89				00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */
90				00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */
91				00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */
92				00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */
93			];
94		};
95
96		partial {
97			gdv = [15];
98			sdv = [41 a8 32];
99			vcom = <0x26>;
100			border-waveform = <0x01>;
101			dummy-line = <0x30>;
102			gate-line-width = <0x0a>;
103			lut = [
104				00 00 00 00 00 00 00 /* LUT0: BB: VS0..6 */
105				80 00 00 00 00 00 00 /* LUT1: BW: VS0..6 */
106				40 00 00 00 00 00 00 /* LUT2: WB: VS0..6 */
107				80 00 00 00 00 00 00 /* LUT3: WW: VS0..6 */
108				00 00 00 00 00 00 00 /* LUT4: VCOM: VS0..6 */
109				0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */
110				00 00 00 00 00 /* TP1A TP1B TP1C TP1D RP1 */
111				00 00 00 00 00 /* TP2A TP2B TP2C TP2D RP2 */
112				00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */
113				00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */
114				00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */
115				00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */
116			];
117		};
118	};
119};
120