1/*
2 * Copyright (c) 2021, Microchip Technology Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <microchip/mec172xnsz.dtsi>
10#include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>
11
12/ {
13	model = "Microchip MEC172XEVB_ASSY6906 evaluation board";
14	compatible = "microchip,mec172xevb_assy6906", "microchip,mec172xnsz";
15
16	chosen {
17		zephyr,sram = &sram0;
18		zephyr,flash = &flash0;
19		zephyr,console = &uart1;
20	};
21
22	aliases {
23		led0 = &led4;
24		led1 = &led3;
25		i2c0 = &i2c_smb_0;
26		i2c-0 = &i2c_smb_0;
27		i2c1 = &i2c_smb_1;
28		i2c7 = &i2c_smb_2;
29		pwm-0 = &pwm0;
30		watchdog0 = &wdog;
31	};
32
33	leds {
34		compatible = "gpio-leds";
35		led4: led_0 {
36			/* GPIO241/CMP_VOUT0/PWM0_ALT on schematic,
37			 * LED4 on silkscreen.
38			 */
39			gpios = <MCHP_GPIO_DECODE_241 GPIO_ACTIVE_HIGH>;
40			label = "LED 4";
41		};
42		led3: led_1 {
43			/* GPIO175/CMP_VOUT1/PWM8_ALT on schematic,
44			 * LED5 on silkscreen.
45			 */
46			gpios = <MCHP_GPIO_DECODE_175 GPIO_ACTIVE_HIGH>;
47			label = "LED 5";
48		};
49	};
50
51	power-states {
52		idle: idle {
53			compatible = "zephyr,power-state";
54			power-state-name = "suspend-to-idle";
55			min-residency-us = <1000000>;
56		};
57
58		suspend_to_ram: suspend_to_ram {
59			compatible = "zephyr,power-state";
60			power-state-name = "suspend-to-ram";
61			min-residency-us = <2000000>;
62		};
63	};
64};
65
66&cpu0 {
67	clock-frequency = <96000000>;
68	status = "okay";
69	cpu-power-states = <&idle &suspend_to_ram>;
70};
71
72/* Initialize ECIA. Does not initialize child devices */
73&ecia {
74	status = "okay";
75};
76
77/* Enable aggregated GIRQ24 and GIRQ25 for eSPI virtual wires interrupts */
78&girq24 {
79	status = "okay";
80};
81
82&girq25 {
83	status = "okay";
84};
85
86&rtimer {
87	status = "okay";
88};
89
90&pcr {
91	status = "okay";
92};
93
94&uart1 {
95	status = "okay";
96	current-speed = <115200>;
97	pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
98	pinctrl-names = "default";
99};
100
101&adc0 {
102	status = "okay";
103	pinctrl-0 = <&adc00_gpio200 &adc03_gpio203
104		     &adc04_gpio204 &adc05_gpio205>;
105	pinctrl-1 = <&adc00_gpio200_sleep &adc03_gpio203_sleep
106		     &adc04_gpio204_sleep &adc05_gpio205_sleep>;
107	pinctrl-names = "default", "sleep";
108};
109
110&espi0 {
111	status = "okay";
112	pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066
113		      &espi_alert_n_gpio063 &espi_clk_gpio065
114		      &espi_io0_gpio070 &espi_io1_gpio071
115		      &espi_io2_gpio072 &espi_io3_gpio073 >;
116	pinctrl-names = "default";
117};
118
119/* enable various eSPI child devices (host facing) */
120&kbc0 {
121	status = "okay";
122};
123
124&acpi_ec0 {
125	status = "okay";
126};
127
128&acpi_ec1 {
129	status = "okay";
130};
131
132&emi0 {
133	status = "okay";
134};
135
136&p80bd0 {
137	status = "okay";
138};
139
140/* I2C */
141&i2c_smb_0 {
142	status = "okay";
143	port_sel = <0>;
144
145	pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;
146	pinctrl-names = "default";
147};
148
149&i2c00_scl_gpio004 {
150	drive-open-drain;
151	output-enable;
152	output-high;
153};
154
155&i2c00_sda_gpio003 {
156	drive-open-drain;
157	output-enable;
158	output-high;
159};
160
161&i2c_smb_1 {
162	status = "okay";
163	port_sel = <1>;
164	pinctrl-0 = <&i2c01_scl_gpio131 &i2c01_sda_gpio130>;
165	pinctrl-names = "default";
166
167	pca9555@26 {
168		compatible = "nxp,pca95xx";
169
170		/* Depends on JP53 for device address.
171		 * Pin 1-2 = A0, pin 3-4 = A1, pin 5-6 = A2.
172		 * Address is: 0100<A2><A1><A0>b.
173		 *
174		 * Default has pin 1-2 on JP53 connected,
175		 * resulting in device address 0x26.
176		 */
177		reg = <0x26>;
178
179		gpio-controller;
180		#gpio-cells = <2>;
181	};
182};
183
184&i2c01_scl_gpio131 {
185	drive-open-drain;
186	output-enable;
187	output-high;
188};
189
190&i2c01_sda_gpio130 {
191	drive-open-drain;
192	output-enable;
193	output-high;
194};
195
196&i2c_smb_2 {
197	status = "okay";
198	port_sel = <7>;
199	pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>;
200	pinctrl-names = "default";
201};
202
203&i2c07_scl_gpio013 {
204	drive-open-drain;
205	output-enable;
206	output-high;
207};
208
209&i2c07_sda_gpio012 {
210	drive-open-drain;
211	output-enable;
212	output-high;
213};
214
215&spi0 {
216	status = "okay";
217	compatible = "microchip,xec-qmspi-ldma";
218	clock-frequency = <4000000>;
219	lines = <4>;
220	chip-select = <0>;
221
222	pinctrl-0 = < &shd_cs0_n_gpio055
223		      &shd_clk_gpio056
224		      &shd_io0_gpio223
225		      &shd_io1_gpio224
226		      &shd_io2_gpio227
227		      &shd_io3_gpio016 >;
228	pinctrl-names = "default";
229};
230
231&kscan0 {
232	status = "okay";
233
234	pinctrl-0 = < &ksi0_gpio017
235		      &ksi1_gpio020
236		      &ksi2_gpio021
237		      &ksi3_gpio026
238		      &ksi4_gpio027
239		      &ksi5_gpio030
240		      &ksi6_gpio031
241		      &ksi7_gpio032
242		      &kso00_gpio040
243		      &kso01_gpio045
244		      &kso02_gpio046
245		      &kso03_gpio047
246		      &kso04_gpio107
247		      &kso05_gpio112
248		      &kso06_gpio113
249		      &kso07_gpio120
250		      &kso08_gpio121
251		      &kso09_gpio122
252		      &kso10_gpio123
253		      &kso11_gpio124
254		      &kso12_gpio125
255		      &kso13_gpio126 >;
256	pinctrl-names = "default";
257};
258
259&ksi0_gpio017 {
260	bias-pull-up;
261};
262
263&ksi1_gpio020 {
264	bias-pull-up;
265};
266
267&ksi2_gpio021 {
268	bias-pull-up;
269};
270
271&ksi3_gpio026 {
272	bias-pull-up;
273};
274
275&ksi4_gpio027 {
276	bias-pull-up;
277};
278
279&ksi5_gpio030 {
280	bias-pull-up;
281};
282
283&ksi6_gpio031 {
284	bias-pull-up;
285};
286
287&ksi7_gpio032 {
288	bias-pull-up;
289};
290
291&pwm0 {
292	status = "okay";
293	pinctrl-0 = <&pwm0_gpio053>;
294	pinctrl-names = "default";
295};
296
297&tach0 {
298	status = "okay";
299	pinctrl-0 = <&tach0_gpio050>;
300	pinctrl-names = "default";
301};
302
303&ps2_0 {
304	status = "okay";
305	pinctrl-0 = <&ps2_clk0a_gpio114 &ps2_dat0a_gpio115>;
306	pinctrl-names = "default";
307};
308
309&timer5 {
310	status = "okay";
311};
312