1# XTENSA architecture configuration options
2
3# Copyright (c) 2016 Cadence Design Systems, Inc.
4# SPDX-License-Identifier: Apache-2.0
5
6menu "XTENSA Options"
7	depends on XTENSA
8
9config ARCH
10	default "xtensa"
11
12config SIMULATOR_XTENSA
13	bool "Simulator Configuration"
14	help
15	  Specify if the board configuration should be treated as a simulator.
16
17config SYS_CLOCK_HW_CYCLES_PER_SEC
18	prompt "Hardware clock cycles per second, 2000000 for ISS"
19	default 2000000
20	range 1000000 1000000000
21	help
22	  This option specifies hardware clock.
23
24config XTENSA_NO_IPC
25	bool "Core has no IPC support"
26	select ATOMIC_OPERATIONS_C
27	help
28	  Uncheck this if your core does not implement "SCOMPARE1" register and "s32c1i"
29	  instruction.
30
31config XTENSA_RESET_VECTOR
32	bool "Build reset vector code"
33	default y
34	help
35	  This option controls whether the initial reset vector code is built.
36	  This is always needed for the simulator. Real boards may already
37	  implement this in boot ROM.
38
39config XTENSA_USE_CORE_CRT1
40	bool "Use crt1.S from core"
41	default y
42	help
43	  SoC or boards might define their own __start by setting this setting
44	  to false.
45
46config XTENSA_ENABLE_BACKTRACE
47	bool "Backtrace on panic exception"
48	default y
49	depends on SOC_ESP32 || SOC_FAMILY_INTEL_ADSP
50	help
51	  Enable this config option to print backtrace on panic exception
52
53config XTENSA_CPU_IDLE_SPIN
54	bool "Use busy loop for k_cpu_idle"
55	help
56	  Use a spin loop instead of WAITI for the CPU idle state.
57
58config XTENSA_WAITI_BUG
59	bool "Workaround sequence for WAITI bug on LX6"
60	help
61	  SOF traditionally contains this workaround on its ADSP
62	  platforms which prefixes a WAITI entry with 128 NOP
63	  instructions followed by an ISYNC and EXTW.
64
65config XTENSA_SMALL_VECTOR_TABLE_ENTRY
66	bool "Workaround for small vector table entries"
67	help
68	  This option enables a small indirection to bypass the size
69	  constraint of the vector table entry and moved the default
70	  handlers to the end of vector table, renaming them to
71	  _Level\LVL\()VectorHelper.
72
73config XTENSA_RPO_CACHE
74	bool "Cached/uncached RPO mapping"
75	help
76	  Support Cached/uncached RPO mapping.
77
78	  A design trick on multi-core hardware is to map memory twice
79	  so that it can be seen in both (incoherent) cached mappings
80	  and a coherent "shared" area.
81
82if XTENSA_RPO_CACHE
83config XTENSA_CACHED_REGION
84	int "Cached RPO mapping"
85	range 0 7
86	help
87	  This specifies which 512M region (0-7, as defined by the Xtensa
88	  Region Protection Option) contains the "cached" mapping.
89
90config XTENSA_UNCACHED_REGION
91	int "Uncached RPO mapping"
92	range 0 7
93	help
94	  As for XTENSA_CACHED_REGION, this specifies which 512M
95	  region (0-7) contains the "uncached" mapping.
96
97endif
98
99config XTENSA_CCOUNT_HZ
100	int "CCOUNT cycle rate"
101	default 1000000
102	help
103	  Rate in HZ of the Xtensa core as measured by the value of
104	  the CCOUNT register.
105
106if CPU_HAS_MMU
107
108config XTENSA_MMU
109	bool "Xtensa MMU Support"
110	default n
111	select MMU
112	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
113	help
114	  Enable support for Xtensa Memory Management Unit.
115
116if XTENSA_MMU
117
118	choice
119		prompt "PageTable virtual adddress"
120		default XTENSA_MMU_PTEVADDR_20000000
121		help
122		  The virtual address for Xtensa page table (PTEVADDR).
123
124	config XTENSA_MMU_PTEVADDR_20000000
125		bool "0x20000000"
126
127	endchoice
128
129	config XTENSA_MMU_PTEVADDR
130		hex
131		default 0x20000000 if XTENSA_MMU_PTEVADDR_20000000
132		help
133		  The virtual address for Xtensa page table (PTEVADDR).
134
135	config XTENSA_MMU_PTEVADDR_SHIFT
136		int
137		default 29 if XTENSA_MMU_PTEVADDR_20000000
138		help
139		  The bit shift number for the virtual address for Xtensa
140		  page table (PTEVADDR).
141
142	config XTENSA_MMU_NUM_L2_TABLES
143		int "Number of L2 page tables"
144		default 10
145		help
146		  Each table can address up to 4MB memory address.
147
148	config XTENSA_MMU_DOUBLE_MAP
149		bool "Map memory in cached and uncached region"
150		default n
151		help
152			This option specifies that the memory is mapped in two
153			distinct region, cached and uncached.
154
155endif # XTENSA_MMU
156
157endif # CPU_HAS_MMU
158
159endmenu
160